Tri gate press foils 0603
High Performance Non-Planar
Tri-gate Transistor Architecture
Ken David
Co-Director, Components Research
Logic Technology Development
Technology and Manufacturing Group
June 4, 2003
Intel
Intel
1
What Are We Announcing?
•
Previously we disclosed the invention of a novel experimental non-planar
Tri-gate transistor structure (Sept 17, 2002 at ISSDM, Nagoya Japan)
•
Since then, improvements have been made and the tri-gate transistor
continues to show higher performance and better scalability than
conventional bulk Si transistor
•
60nm tri-gate transistor achieves world-record non-planar NMOS
performance and low leakage*
•
Scalability to 30nm gate length has also been demonstrated
•
These tri-gate transistors were fabricated in D1C, which is our 300mm
development and manufacturing Fab in Oregon for the 90nm process
generation
−
Tri-gate basic process steps are similar to the current baseline
manufacturing process
•
Tri-gate transistor has gone beyond the research phase and is now
entering the development phase
•
Tri-gate transistor allows Moore’s Law to continue and is one of the key
transistor options being evaluated for Intel’s 45nm process generation
(2007 production)
Intel
Intel
* IDsat = 1.23mA/um and Ioff = 40nA/um at Vcc = 1.3V
2
Transistor Architectures
Lg
Source
Gate
Drain
Si
T Si
(Planar)
Drain
Isolation
Gate 3
TSi
Lg
Gate 1
Source
Lg
Gate 1
Source
WSi
Drain
WSi
TSi
Gate 2
Gate 2
Double-gate (e.g. FINFET)
Intel
Intel (Non-Planar)
Tri-gate
(Non-Planar)
3
Tri-gate Transistor
Top Gate
Actual photo
30nm Tri-gate transistor
Side Gate
Source
Drain
Side Gate
Simulation
Cross-section of
silicon channel
shows much more
current flow
(indicated by red) in
tri-gate transistor
than in planar
transistor
Intel
Intel
Tri-Gate
Tri-Gate
Conventional
Planar
Planar
4
World Record Non-Planar Performance
Very high drive current at saturation, 1.23 mA/µm
Very low
leakage,
40nA/µm
Drain current (amps/µm)
1E-02
1E-03
Drain voltage=1.3V
1E-04
Drain voltage=0.05V
1E-05
1E-06
1E-07
1E-08
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Gate voltage (Volts)
Tri-gate transistor exhibits excellent device
characteristics
Intel
Intel
5
Additional details of the Tri-gate transistor design and
technology will be presented at the 2003 Symposium
on VLSI Technology in Kyoto Japan on June 12, 2003
For further information on Intel's silicon technology,
please visit the Silicon Showcase at
www.intel.com/research/silicon
Intel
Intel
6
Tri-gate Transistor Architecture
Ken David
Co-Director, Components Research
Logic Technology Development
Technology and Manufacturing Group
June 4, 2003
Intel
Intel
1
What Are We Announcing?
•
Previously we disclosed the invention of a novel experimental non-planar
Tri-gate transistor structure (Sept 17, 2002 at ISSDM, Nagoya Japan)
•
Since then, improvements have been made and the tri-gate transistor
continues to show higher performance and better scalability than
conventional bulk Si transistor
•
60nm tri-gate transistor achieves world-record non-planar NMOS
performance and low leakage*
•
Scalability to 30nm gate length has also been demonstrated
•
These tri-gate transistors were fabricated in D1C, which is our 300mm
development and manufacturing Fab in Oregon for the 90nm process
generation
−
Tri-gate basic process steps are similar to the current baseline
manufacturing process
•
Tri-gate transistor has gone beyond the research phase and is now
entering the development phase
•
Tri-gate transistor allows Moore’s Law to continue and is one of the key
transistor options being evaluated for Intel’s 45nm process generation
(2007 production)
Intel
Intel
* IDsat = 1.23mA/um and Ioff = 40nA/um at Vcc = 1.3V
2
Transistor Architectures
Lg
Source
Gate
Drain
Si
T Si
(Planar)
Drain
Isolation
Gate 3
TSi
Lg
Gate 1
Source
Lg
Gate 1
Source
WSi
Drain
WSi
TSi
Gate 2
Gate 2
Double-gate (e.g. FINFET)
Intel
Intel (Non-Planar)
Tri-gate
(Non-Planar)
3
Tri-gate Transistor
Top Gate
Actual photo
30nm Tri-gate transistor
Side Gate
Source
Drain
Side Gate
Simulation
Cross-section of
silicon channel
shows much more
current flow
(indicated by red) in
tri-gate transistor
than in planar
transistor
Intel
Intel
Tri-Gate
Tri-Gate
Conventional
Planar
Planar
4
World Record Non-Planar Performance
Very high drive current at saturation, 1.23 mA/µm
Very low
leakage,
40nA/µm
Drain current (amps/µm)
1E-02
1E-03
Drain voltage=1.3V
1E-04
Drain voltage=0.05V
1E-05
1E-06
1E-07
1E-08
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Gate voltage (Volts)
Tri-gate transistor exhibits excellent device
characteristics
Intel
Intel
5
Additional details of the Tri-gate transistor design and
technology will be presented at the 2003 Symposium
on VLSI Technology in Kyoto Japan on June 12, 2003
For further information on Intel's silicon technology,
please visit the Silicon Showcase at
www.intel.com/research/silicon
Intel
Intel
6