VLSI 90nm foils 0604
Delaying Forever:
Uniaxial Strained Silicon Transistors
in a 90nm CMOS Technology
K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan,
T. Ghani, T. Hoffman, A. Murthy, J. Sandford,
R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson#,
M. Bohr
Logic Technology Development
Intel Corporation
#now
with University of Florida
Key Messages
• Biaxial vs. Uniaxial strain
– Electron mobility gain similar for both stress types
– Hole mobility gain superior for uniaxial strain
• Epitaxial S/D transistor structure
– Large uniaxial strain
– Improved REXT so full mobility benefit is realized
• This is a high volume manufacturing
technology
2
Outline
• Introduction
• Why Uniaxial Strain?
• Transistor Results
• Performance & Power
• Summary
3
Transistor Scaling: The Mobility Challenge
• Mobility degrades with transistor scaling
Electron Mobility (cm2/V s)
– Universal mobility model
– Ionized impurity scattering
1000
EEFF-2
EEFF- 0.3
100
Source: Intel Technology
10
0.1
1
EEFF (MV/cm)
10
4
Strain Enhanced Mobility
• Strain can be used to enhance mobility
Electron Mobility (cm2/V s)
– Effect known for >50 years [C.S. Smith, Phys Rev, 1954]
1000
EEFF-2
EEFF- 0.3
100
Source: Intel Technology
10
0.1
1
EEFF (MV/cm)
10
5
Biaxial Tensile Strain
Biaxial tensile strain studied extensively last 10 years
– Large electron mobility gain, but...
n+
Gate
Two key problems:
1. Integration difficulties
–
–
–
–
Dislocations
STI
Ge Up-diffusion
Fast diffusion of extensions
Cost
2. Poor hole mobility gain
S
Strained Si
D
Relaxed Si1-xGex
Graded Si1-yGey
Si Substrate
6
Outline
• Introduction
• Why Uniaxial Strain?
• Transistor Results
• Performance & Power
• Summary
7
Biaxial vs. Uniaxial Strain: Electrons
• Electron mobility enhancement similar
– Both cases result from splitting of 6-fold degenerate valleys
– Only valley shifting responsible for mobility gain
– Negligible band curvature change in either case
∆2
∆4
8
Biaxial vs. Uniaxial Strain: Holes
• Uniaxial stress more effective than biaxial for
hole mobility improvement
– Simple calculations using peizoresistance coefficients
[C.S. Smith, Phys. Rev., 1954]
40
channel orientation
(001 surface)
% Hole ∆µ / µ
35
30
Longitudinal compressive
25
20
Tranverse tensile
15
10
Compressive stress ~12.5 % Ge
(Biaxial in plane tension)
5
0
0
200
400
σ / Stress MPa
600
9
Biaxial vs. Uniaxial Strain: Holes
• Biaxial strain: hole mobility gain lost at high EEFF
LH
HH
Mobility / cm / (V*Sec)
– Mobility gain due to lower scattering: separation of LH & HH bands
Î Not due to reduction in hole effective mass
– At high EEFF LH – HH separation reduced due to quantization
Î Hole mobility gain is lost
140
Rim
et al
1995
120
100
Biaxial Strain
80
Universal Hole
Mobility
60
Rim et al.
2002
40
Strain
Quantization
Low EEFF High EEFF
0
0.2
0.4
0.6
0.8
EEFF / (MV/cm)
1
1.2
10
Biaxial vs. Uniaxial Strain: Holes
• Uniaxial strain: high hole mobility at high EEFF
Mobility / cm / (V*Sec)
– Mobility gain from effective mass reduction
Î Change in band warping [Giles, VLSI04]
– Band separation not reduced at high EEFF
Î High out of plane effective mass for light holes
140
Rim
et al
1995
120
Uniaxial Strain
100
80
Universal Hole
Mobility
60
Rim et al.
2002
40
0
0.2
0.4
0.6
0.8
EEFF / (MV/cm)
1
1.2
11
Outline
• Introduction
• Why Uniaxial Strain?
• Transistor Results
• Performance & Power
• Summary
12
Uniaxial Strain Structures
• Two uniaxial strain structures incorporated in
our 90nm CMOS technology
– Epitaxial S/D Transistor for PMOS
– Tensile capping layer for NMOS
High Stress Film
SiGe
SiGe
13
Transistor Results: PMOS
• Astounding PMOS drive current of 0.72 mA/µm!
– at 1.2V and IOFF = 40nA/µm
– 30% IDSAT gain from strain enhanced mobility
IOFF (nA/um)
1000
100
1.0V
1.2V
40nA/um
10
1
0.1
0.4
0.5
0.6
0.7
IDSAT (mA/um)
0.8
0.9
14
Transistor Results: Channel Strain
• Simulations show Epitaxial
S/D transistor has uniaxial
compressive channel strain
-0.1
0
Channel
-200
[Giles VLSI04]
– Predicts 55% hole mobility gain
-400
0
• TEM electron diffraction
measurements confirm 0.6%
lattice displacement
-600
SiGe
-800
-1000
LGATE=50nm
0.1
0
0.1
15
Transistor Results: IDLIN & Strain
• IDLIN gain vs. LGATE correlated to stress from 2.0µm to 0.1µm
• Both REXT and strain contribute to gain for < 0.1µm
• Net IDLIN gain of 55% vs. simulated mobility gain of 55%
– Full mobility gain seen in IDLIN; Epi S/D transistor also improves REXT
600
% IDlin Gain
80
500
60
400
40
300
200
20
100
Improved REXT
SiGe
SiGe
0
0
0.01
Average SXX [MPa]
700
100
0.1
1
Gate Length [um]
10
Improved Mobility
16
Transistor Results: Pattern Dependence
• PMOS IDSAT for min. poly pitch vs. wider pitch
– Initial results showed a large difference
– Minimized with process optimization
% IDSAT MISMATCH
25
20
15
10
5
0
Process 1
Process 2
Process 3
17
Transistor Results: NMOS
• Record NMOS drive current of 1.26 mA/um
– 10% IDSAT gain from tensile strain layer
1000
IOFF (nA/um)
1.0V
100
1.2V
40nA/um
10
1
0.8
0.9
1
1.1 1.2 1.3
IDSAT (mA/um)
1.4
1.5
18
Transistor Results: CMOS
15
15
10
10
5
5
0
0
0
20
40
60
Cap Thickness (nm)
PMOS IDSAT Loss (%)
NMOS IDSAT Gain (%)
• Tensile capping layer improves NMOS IDSAT
with no significant PMOS IDSAT loss
80
19
Outline
• Introduction
• Why Uniaxial Strain?
• Transistor Results
• Performance & Power
• Summary
20
Performance
• Strained silicon results in fast ring oscillators
– Delay per stage of 4.6pS for low VT devices
Delay (pS)
7
6
HiVT
LoVT
5
4
10
100
1000
10000
IOFF-N + IOFF-P (nA/um)
21
Power: Leakage Reduction
• Strained silicon: high performance, low power
– Performance: 30% IDSAT gain at fixed IOFF
– Power:
50X lower IOFF at fixed IDSAT
1000
IOFF (nA/um)
Control
30%
100
Strained
50X
10
1
0.1
0.4
0.5
0.6
0.7
IDSAT (mA/um)
0.8
0.9
22
Power: SRAM VCCmin
• Strain silicon also improves SRAM VCCmin
– Important for long battery life in mobile applications
– Strain enhanced PMOS balances VT mismatch in NMOS
– 50Mb SRAM with 1.0µm2 cell functional down to 0.65V
Strain
enhanced
PMOS
1
VDD (V)
0.9
0.8
0.7
VT
mismatch
induced
leakage
0.6
FAIL
0.6
3.0
Cycle Time (ns)
23
Summary
• Uniaxial strain has significant advantages over
biaxial strain for hole mobility enhancement
• Epitaxial S/D transistor structure provides
– Large uniaxial channel strain
– >50% hole mobility gain and lower REXT
– IDLIN sees ALL the mobility gain due to lower REXT
• Strained silicon allows for improved
performance and lower power dissipation
24
Delaying Forever…
• New materials & structures can extend Moore’s law
– Strained silicon is a key example
No exponential is
forever. Your job
is to delay forever.
Gate Length (nm)
1000
100
Gordon
Moore
10
1990
1995
2000
2005
2010
25
Acknowledgements
The authors gratefully acknowledge the many
people at Intel who contributed to the successful
implementation of strained silicon for the 90nm
CMOS technology node, including individuals
from the following organizations:
• Portland Technology Development
• Technology Computer Aided Design
• Quality and Reliability Engineering
26
For further information on Intel’s silicon technology
please visit the Silicon Showcase at
www.intel.com/research/silicon
27
Uniaxial Strained Silicon Transistors
in a 90nm CMOS Technology
K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan,
T. Ghani, T. Hoffman, A. Murthy, J. Sandford,
R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson#,
M. Bohr
Logic Technology Development
Intel Corporation
#now
with University of Florida
Key Messages
• Biaxial vs. Uniaxial strain
– Electron mobility gain similar for both stress types
– Hole mobility gain superior for uniaxial strain
• Epitaxial S/D transistor structure
– Large uniaxial strain
– Improved REXT so full mobility benefit is realized
• This is a high volume manufacturing
technology
2
Outline
• Introduction
• Why Uniaxial Strain?
• Transistor Results
• Performance & Power
• Summary
3
Transistor Scaling: The Mobility Challenge
• Mobility degrades with transistor scaling
Electron Mobility (cm2/V s)
– Universal mobility model
– Ionized impurity scattering
1000
EEFF-2
EEFF- 0.3
100
Source: Intel Technology
10
0.1
1
EEFF (MV/cm)
10
4
Strain Enhanced Mobility
• Strain can be used to enhance mobility
Electron Mobility (cm2/V s)
– Effect known for >50 years [C.S. Smith, Phys Rev, 1954]
1000
EEFF-2
EEFF- 0.3
100
Source: Intel Technology
10
0.1
1
EEFF (MV/cm)
10
5
Biaxial Tensile Strain
Biaxial tensile strain studied extensively last 10 years
– Large electron mobility gain, but...
n+
Gate
Two key problems:
1. Integration difficulties
–
–
–
–
Dislocations
STI
Ge Up-diffusion
Fast diffusion of extensions
Cost
2. Poor hole mobility gain
S
Strained Si
D
Relaxed Si1-xGex
Graded Si1-yGey
Si Substrate
6
Outline
• Introduction
• Why Uniaxial Strain?
• Transistor Results
• Performance & Power
• Summary
7
Biaxial vs. Uniaxial Strain: Electrons
• Electron mobility enhancement similar
– Both cases result from splitting of 6-fold degenerate valleys
– Only valley shifting responsible for mobility gain
– Negligible band curvature change in either case
∆2
∆4
8
Biaxial vs. Uniaxial Strain: Holes
• Uniaxial stress more effective than biaxial for
hole mobility improvement
– Simple calculations using peizoresistance coefficients
[C.S. Smith, Phys. Rev., 1954]
40
channel orientation
(001 surface)
% Hole ∆µ / µ
35
30
Longitudinal compressive
25
20
Tranverse tensile
15
10
Compressive stress ~12.5 % Ge
(Biaxial in plane tension)
5
0
0
200
400
σ / Stress MPa
600
9
Biaxial vs. Uniaxial Strain: Holes
• Biaxial strain: hole mobility gain lost at high EEFF
LH
HH
Mobility / cm / (V*Sec)
– Mobility gain due to lower scattering: separation of LH & HH bands
Î Not due to reduction in hole effective mass
– At high EEFF LH – HH separation reduced due to quantization
Î Hole mobility gain is lost
140
Rim
et al
1995
120
100
Biaxial Strain
80
Universal Hole
Mobility
60
Rim et al.
2002
40
Strain
Quantization
Low EEFF High EEFF
0
0.2
0.4
0.6
0.8
EEFF / (MV/cm)
1
1.2
10
Biaxial vs. Uniaxial Strain: Holes
• Uniaxial strain: high hole mobility at high EEFF
Mobility / cm / (V*Sec)
– Mobility gain from effective mass reduction
Î Change in band warping [Giles, VLSI04]
– Band separation not reduced at high EEFF
Î High out of plane effective mass for light holes
140
Rim
et al
1995
120
Uniaxial Strain
100
80
Universal Hole
Mobility
60
Rim et al.
2002
40
0
0.2
0.4
0.6
0.8
EEFF / (MV/cm)
1
1.2
11
Outline
• Introduction
• Why Uniaxial Strain?
• Transistor Results
• Performance & Power
• Summary
12
Uniaxial Strain Structures
• Two uniaxial strain structures incorporated in
our 90nm CMOS technology
– Epitaxial S/D Transistor for PMOS
– Tensile capping layer for NMOS
High Stress Film
SiGe
SiGe
13
Transistor Results: PMOS
• Astounding PMOS drive current of 0.72 mA/µm!
– at 1.2V and IOFF = 40nA/µm
– 30% IDSAT gain from strain enhanced mobility
IOFF (nA/um)
1000
100
1.0V
1.2V
40nA/um
10
1
0.1
0.4
0.5
0.6
0.7
IDSAT (mA/um)
0.8
0.9
14
Transistor Results: Channel Strain
• Simulations show Epitaxial
S/D transistor has uniaxial
compressive channel strain
-0.1
0
Channel
-200
[Giles VLSI04]
– Predicts 55% hole mobility gain
-400
0
• TEM electron diffraction
measurements confirm 0.6%
lattice displacement
-600
SiGe
-800
-1000
LGATE=50nm
0.1
0
0.1
15
Transistor Results: IDLIN & Strain
• IDLIN gain vs. LGATE correlated to stress from 2.0µm to 0.1µm
• Both REXT and strain contribute to gain for < 0.1µm
• Net IDLIN gain of 55% vs. simulated mobility gain of 55%
– Full mobility gain seen in IDLIN; Epi S/D transistor also improves REXT
600
% IDlin Gain
80
500
60
400
40
300
200
20
100
Improved REXT
SiGe
SiGe
0
0
0.01
Average SXX [MPa]
700
100
0.1
1
Gate Length [um]
10
Improved Mobility
16
Transistor Results: Pattern Dependence
• PMOS IDSAT for min. poly pitch vs. wider pitch
– Initial results showed a large difference
– Minimized with process optimization
% IDSAT MISMATCH
25
20
15
10
5
0
Process 1
Process 2
Process 3
17
Transistor Results: NMOS
• Record NMOS drive current of 1.26 mA/um
– 10% IDSAT gain from tensile strain layer
1000
IOFF (nA/um)
1.0V
100
1.2V
40nA/um
10
1
0.8
0.9
1
1.1 1.2 1.3
IDSAT (mA/um)
1.4
1.5
18
Transistor Results: CMOS
15
15
10
10
5
5
0
0
0
20
40
60
Cap Thickness (nm)
PMOS IDSAT Loss (%)
NMOS IDSAT Gain (%)
• Tensile capping layer improves NMOS IDSAT
with no significant PMOS IDSAT loss
80
19
Outline
• Introduction
• Why Uniaxial Strain?
• Transistor Results
• Performance & Power
• Summary
20
Performance
• Strained silicon results in fast ring oscillators
– Delay per stage of 4.6pS for low VT devices
Delay (pS)
7
6
HiVT
LoVT
5
4
10
100
1000
10000
IOFF-N + IOFF-P (nA/um)
21
Power: Leakage Reduction
• Strained silicon: high performance, low power
– Performance: 30% IDSAT gain at fixed IOFF
– Power:
50X lower IOFF at fixed IDSAT
1000
IOFF (nA/um)
Control
30%
100
Strained
50X
10
1
0.1
0.4
0.5
0.6
0.7
IDSAT (mA/um)
0.8
0.9
22
Power: SRAM VCCmin
• Strain silicon also improves SRAM VCCmin
– Important for long battery life in mobile applications
– Strain enhanced PMOS balances VT mismatch in NMOS
– 50Mb SRAM with 1.0µm2 cell functional down to 0.65V
Strain
enhanced
PMOS
1
VDD (V)
0.9
0.8
0.7
VT
mismatch
induced
leakage
0.6
FAIL
0.6
3.0
Cycle Time (ns)
23
Summary
• Uniaxial strain has significant advantages over
biaxial strain for hole mobility enhancement
• Epitaxial S/D transistor structure provides
– Large uniaxial channel strain
– >50% hole mobility gain and lower REXT
– IDLIN sees ALL the mobility gain due to lower REXT
• Strained silicon allows for improved
performance and lower power dissipation
24
Delaying Forever…
• New materials & structures can extend Moore’s law
– Strained silicon is a key example
No exponential is
forever. Your job
is to delay forever.
Gate Length (nm)
1000
100
Gordon
Moore
10
1990
1995
2000
2005
2010
25
Acknowledgements
The authors gratefully acknowledge the many
people at Intel who contributed to the successful
implementation of strained silicon for the 90nm
CMOS technology node, including individuals
from the following organizations:
• Portland Technology Development
• Technology Computer Aided Design
• Quality and Reliability Engineering
26
For further information on Intel’s silicon technology
please visit the Silicon Showcase at
www.intel.com/research/silicon
27