Chau DRC 062303 foils

(1)

Silicon Nano-Transistors and Breaking

the 10nm Physical Gate Length Barrier

Robert Chau, Brian Doyle, Mark Doczy,

Suman Datta, Scott Hareland, Ben Jin,

Jack Kavalieros and Matthew Metz

Components Research

Logic Technology Development

Intel Corporation

June 24 2003

(2)

Content

• Introduction

• Device Scaling trends and the 10nm L

barrier

• New Device Structures

• Gate Dielectric Scaling

(3)

Moore’s Law Continues…

– Transistor # doubling every 2 years toward the 1 billion transistor microprocessor

1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000

1970 1980 1990 2000 2010

4004

8080 8086

8008

Pentium® Processor 486™ DX Processor

386™ Processor 286

Pentium® II Processor Pentium® III Processor

Pentium® 4 Processor

Heading toward 1 billion transistors in 2007

42 Million

(4)

Transistor Physical Gate Length Requirement

0.01 0.10 1.00

1990 1995 2000 2005 2010

Year

Mi

c

ro

n

Technology Node

Transistor Physical Gate

Length

0.5µm

0.35µm

0.25µm

0.18µm

0.13µm

90nm

65nm

45nm

30nm

130nm

70nm

50nm

30nm

20nm _15nm 0.2µm

Transistor physical gate length will reach ~15nm before end of this decade, and ~10nm early next decade

(5)

Conventional Si Transistor Scaling

60nm

Lg = 30nm

L_G= 10nm

65nm Node

45nm node

(6)

Content

• Introduction

• Device Scaling trends and the 10nm L

barrier

• New Device Structures

• Gate Dielectric Scaling

• Summary

(7)

Gate Delay and Energy-Delay Trends

1.E-02 1.E-01 1.E+00 1.E+01

0.001 0.01 0.1 1

LG (µm)

G a te D e la y (p s ) 10nm 20nm 15nm 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03

0.001 0.01 0.1 1

L_G (µm)

E n e rg y -D el ay P ro d u c t (x 10 -2 7 j o ul es .s ec ) 20nm 10nm 15nm

Data from 20nm, 15nm and 10nm research transistors follow the projected trends

(8)

Experimental 15nm Si Nano-Transistor

0 100 200 300 400 500

0 0.2 0.4 0.6 0.8

Drain Voltage (V)

Drain Current (µ A /µ m )

Vg = 0.8V

0.7V 0.6V 0.5V 0.4V 0.3V 15nm NMOS 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

0 0.2 0.4 0.6 0.8

Gate Voltage (V)

Drain Current (A/

Vd = 0.8V

Vd = 0.05V

S.S. = 95mV/decade DIBL = 100mV/V Ioff = 180nA/um 15nm NMOS

• Electrostatics of 15nm transistor remains intact

• Idsat performance can be further improved using thinner Toxe and various enhancement techniques

(9)

Experimental 10nm MOS Transistor

L_G = 10nm 0

200 400 600

0 0.2 0.4 0.6 0.8

Drain Voltage (V)

Drain Current (A/

0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.60.6 0.8

0.75V 0.65V 0.55V 0.45V 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

-0.3 0.0 0.3 0.6 0.9 Gate Voltage (V)

Id ( A /¬ m) `

•

10nm transistor shows degraded short channel performance

− high I_off

0.75V 0.05V

(10)

Transistor Off-state Leakage Trend

1.E-14 1.E-12 1.E-10 1.E-08 1.E-06 1.E-04

10 100 1000

Lg (nm)

Ioff

(A/um)

Intel 10nm device

Intel 15nm device Production Data

(11)

Leakage Power is becoming a

Larger % of Total Chip Power

-Total Power (Watts)

10

100 1,000

0.25u 0.18u 0.13u 90nm 65nm 45nm

Off-State Leakage Active Power

2V 1.7V 1.5V 1.2V 1V 0.9V

Total Power (Watts)

10

100 1,000

0.25u 0.18u 0.13u 90nm 65nm 45nm

Off-State Leakage Power Active Power

2V 1.7V 1.5V 1.2V 1V 0.9V

-Reference: V. De and S. Borkar, “Technology and Design Challenges for Low Power and High Performance,” 1999 ISLPED_{, pp. 163-168, August 1999.}

(12)

Potential Solutions to Transistor

I

_off

Problem

• Low-temperature operation

• _{Improve short-channel performance}

(subthreshold slope & DIBL) using

novel device structures

–

_{Fully-Depleted Transistors}

• Single-gate planar fully depleted SOI

• Double-gate FINFET

(13)

Content

• Introduction

• Device Scaling trends and the 10nm L

barrier

• New Device Structures

• Gate Dielectric Scaling

• Summary

(14)

Si TSi

L_g

Si T

Planar fully depleted SOI

Fully Depleted Transistors

Double-gate (e.g. FINFET)

W

_Si

L

T_Si

Isolation

(Non-Planar)

(Planar)

W

_Si

L

T

_Si

Tri-gate

(Non-Planar)

• Fully depleted transistors provide better short channel performance (steeper subthreshold slope and smaller DIBL)

(15)

Planar Fully Depleted Transistors

Si T_Si

SiO2

1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03

0 0.25 0.5 0.75 1 1.25

VG (Volts)

(A/

DST

Bulk Silicon

V_D = 1.3V

VD = 0.05V

FD-SOI

Planar Fully Depleted SOI

• Fully depleted SOI provides steeper subthreshold slope

and better DIBL, which can be used to reduce Ioff or increase Idsat

• Cost and controllability of thin Si (T_Si) layer are key manufacturing problems

(16)

Planar Fully-depleted SOI

Lg = 60nm

Epi Raised S-D

T

~18 nm

Silicide

BOX

Raised S-D using Selective Epi-Si Deposition

(17)

Tri-gate Transistor

W_Si

L

Top Gate

Side Gate Side Gate

T

_Si S/D

D/S

Gate

Top Gate Side Gate

Side Gate

Body controlled on three sides by adjacent

Gates: Excellent electrostatic control of body

(18)

Si TSi

Lg Si T W_Si

L

_g T_Si W_Si L_g T_Si

0 20 40 60 80

Device Gate Length, Lg (nm)

Silicon Body Thickness

(nm

)

Single-Gate

Double-Tri-Gate

0 20 40 60 80

Single- Gate

Tri-Gate

0 20 40 60 80

-0 10 20 30 40 50

0 20 40 60 80

Double-Gate

-60

(T_Si) (W_Si) (T_Si, W_Si)

1.5X

Tri-gate has the Least Stringent Thickness

& Width Requirements

(19)

VG(Volts)

1E 09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03

-1.4 -1 -0.6 0.6 1 1.4

I d

(|A/

m|)

Vd=-0.05V Vd= 0.05V

Vd=1.3V

-0.2 0.2

nMOS pMOS

Vd=-1.3V

Non-Planar Tri-Gate CMOS Transistor

Silicon Body Buried Oxide 36 nm 55 nm Poly

Lg = 60nm

Silicon Body Buried Oxide 36 nm 55 nm Poly

Lg = 60nm

L_G = 60nm

Lg = 60nm

T_Si= 36 nm

W_Si= 55 nm

Current per unit width = I_d/(2*T_Si+W_Si)

DIBL < 50mV/V, S.S. ~ 69mV/decade

• Excellent electrostatics and good device

performance

(20)

Tri-Gate Device Physics

• _{Three distinct regions of operation}

Oxide

Top channel

Sidewall channel

Corners

(21)

Components of Current in Tri-Gate

Vg (V)

Id (A/

µ

m)

1.0E-09

01.0E-8

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

0.0

0.2

0.4

0.6

0.8

1.0 Non-Corner

Total

Corner

Vd=1.0V

Vd=0.05V

Corner device shows much improved ∆S & DIBL over non-corner devices because of proximity of adjacent gates

(22)

Physics of Corner Device

Vg=0.5V, Vd=1.0V Cut at midpoint along channel

Proximity of the two gates at the corner give the

nearly-ideal characteristics of the corner device, and the high current density

(23)

Tri-Gate Architecture

Gate Si Legs

Gate

Silicon Legs

S D

G

Multiple

Legs

Total Drive Current =

I_dper Tri-gate Transistor x no. of Legs

S D

G

Source

Drain Gate

•

Tri-Gate architecture compatible with future devices such as nanowires and nanotubes

(24)

Nano-Device Structure Evolution

Gate

Nanowire

Non-Planar Tri-gate

Gate

GateGate

Silicon Substrate

SiO2

Gate

Silicon Substrate

SiO2

Planar Transistor

S D

Gate

(25)

Content

• Introduction

• Device Scaling trends and the 10nm L

barrier

• New Device Structures

• Gate Dielectric Scaling

• Summary

(26)

SiO2 Less Than 3 Atomic layers Thick

PolySi

Silicon PolySi

Silicon

SiO2

•

_{SiO2 leakage is increasing with reducing thickness}

•

_{SiO2 gate oxide running out of atoms for further scaling} 0.0

0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg C a pacita nce ( µ F/cm²) NMOS PMOS NMOS PMOS --0.0 0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg (V) Capacit a nce ( µ F/cm²) _NMOS PMOS NMOS PMOS 0.8nm 0.8nm Inversion Capacitance

(27)

Alternative Gate Dielectric Required for

Future-Generation Si Nano-Transistors

1.E-06 1.E-04 1.E-02 1.E+00 1.E+02 1.E+04

5 10 15 20 25

EOT [A]

[A/cm

2 ]

SiO₂ Dielectric

High-K

Dielectric

(28)

NMOS: Ft = 83GHz Fmax = 35GHz

PMOS: Ft = 41GHz Fmax = 25GHz

Si CMOS Transistor with Alternative

Gate Dielectrics

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

-1.5 -1 -0.5 0 0.5 1 1.5

Vds (V)

Ids

(mA/

V_gs-V_th= 1.25V

V_gs-V_th= 0.75V

V_gs-V_th= 0.25V V_gs-V_th= -1.25V

V_gs-V_th= -0.75V V_gs-V_th= -0.25V

PMOS NMOS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

-1.5 -1 -0.5 0 0.5 1 1.5

Vds (V)

Ids

(mA/

V_gs-V_th= 1.25V

V_gs-V_th= 0.75V

V_gs-V_th= 0.25V V_gs-V_th= -1.25V

V_gs-V_th= -0.75V V_gs-V_th= -0.25V

PMOS NMOS

(29)

Summary

• Research Si nano-transistors down to 10nm physical L_G

have been demonstrated with improved intrinsic gate delay and energy-delay trends over devices with longer L_G

• Transistor off-state leakage increases with reducing

physical L_G, and will need to be reduced for future logic products

– 10nm research transistor exhibits degraded short channel performance and high off-state leakage

• Gate oxide leakage is increasing with reducing thickness and SiO2 is running out of atoms for further scaling

• The short-channel performance and off-state leakage of future Si nano-transistors will be improved using new transistor structure such as Tri-gate, and the gate oxide leakage will be reduced using alternative gate stacks

(1)

Nano-Device Structure Evolution

Gate

Nanowire

Non-Planar Tri-gate

Gate

GateGate

SiO2

Gate

SiO2

S D

(2)

Content

• Introduction

• Device Scaling trends and the 10nm L

barrier

• New Device Structures

• Gate Dielectric Scaling

(3)

SiO2 Less Than 3 Atomic layers Thick

PolySi

Silicon

PolySi

Silicon

SiO2

0.0 0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg C a pacita nce ( µ F/cm²) NMOS PMOS NMOS PMOS --0.0 0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg (V) Capacit a nce ( µ F/cm²) _NMOS PMOS NMOS PMOS 0.8nm 0.8nm Inversion Capacitance

(4)

Alternative Gate Dielectric Required for

Future-Generation Si Nano-Transistors

1.E-06 1.E-04 1.E-02 1.E+00 1.E+02 1.E+04

5 10 15 20 25

EOT [A]

[A/cm

2 ]

SiO₂ Dielectric

High-K

Dielectric

(5)

Si CMOS Transistor with Alternative

Gate Dielectrics

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

-1.5 -1 -0.5 0 0.5 1 1.5

Vds (V)

Ids

(mA/

V_gs-V_th= 1.25V

V_gs-V_th= 0.75V

V_gs-V_th= 0.25V

V_gs-V_th= -1.25V

V_gs-V_th= -0.75V

V_gs-V_th= -0.25V

PMOS NMOS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

-1.5 -1 -0.5 0 0.5 1 1.5

Vds (V)

Ids

(mA/

V_gs-V_th= 1.25V

V_gs-V_th= 0.75V

V_gs-V_th= 0.25V

V_gs-V_th= -1.25V

V_gs-V_th= -0.75V

V_gs-V_th= -0.25V

PMOS NMOS

(6)

Summary

• Research Si nano-transistors down to 10nm physical L_G

have been demonstrated with improved intrinsic gate delay

and energy-delay trends over devices with longer L_G

• Transistor off-state leakage increases with reducing

physical L_G, and will need to be reduced for future logic

products

– 10nm research transistor exhibits degraded short

channel performance and high off-state leakage

• Gate oxide leakage is increasing with reducing thickness

and SiO2 is running out of atoms for further scaling

• The short-channel performance and off-state leakage of

future Si nano-transistors will be improved using new transistor structure such as Tri-gate, and the gate oxide leakage will be reduced using alternative gate stacks