Third Year - Microprocessors By Mr.WaleedFawwaz
Maximum mode signalsMN MX
����=Ground Name
Function Type
RQGT1,0 ������������� Requestgrant bus
access control Bidirectional
LOCK �������
Bus priority lock control
Output, 3-state S2
��� − S0 ���
Bus cycle status Output, 3-state
QS1, QS0 Instruction queue
status Output
c
Figure 2 a signals common to both minimum and maximum mode. b Unique
minimum-mode signals. c Unique maximum-mode signals. Minimum mode interface signals
The minimum-mode signals can be divided into the following basic groups:
1. The address bus is 20 bits long and consists of signal lines A
AddressData Bus
the LSB to A
19
the MSB. The data bus is 16 bits long and consists of signals lines D
the LSB to D
15
2.
the MSB. When acting as a data bus, they carry readwrite data for memory,
inputoutput data for IO devices, and interrupt-type codes from an interrupt controller.
The four most significant address lines, A
Status signals
19
through A
16
are also multiplexed, but with status signals S
6
through S
3
. These status bits are output on the bus at the same time that data are transferred over the other bus lines. Bits S
4
and S
3
together form a 2-bit binary code that identifies which of the internal segment registers was used to generate the physical address that was output on the
address bus during the current bus cycle See Figure 3 S
4
S
3
Address Status
alternaterelative to the ES segment
1 Stack relative to the SS segment
1 CodeNone relative to the CS segment or a default of zero
1 1
Data relative to the DS segment
Figure 3 address bus status codes Status line S
5
3.
reflects the status of logic level of the internal interrupt enable flag.
These are provided to support the memory and IO interfaces of the 8086.
The control signals • ALE signal: is a pulse to logic 1 that signals external circuitry when a
valid address is on the bus. This address can be latched in external circuitry on the 1-to-0 edge pulse at ALE.
Third Year - Microprocessors By Mr.WaleedFawwaz
• M�� ��� signal: tells external circuitry whether a memory or IO transfer is
taking place over the bus. Logic 1 for memory operation, logic 0 for IO operation.
• DT�� signal: when this line is logic 1 the bus is in Transmit Mode data
are either written into memory or output to an IO device. When this line is logic 0 the bus is in Receive Mode data are either read from
memory or input to an IO device.
• ���
������signal: logic 0 on this line is used as a memory enable signal for the most significant byte half of the data bus, D
8
through D • ��
����signal: indicate that a read bus cycle is in progress.
15.
• ��
�����signal: indicate that a write bus cycle is in progress.
• ���
������signal:during read operations, this signal is also supplied to enables external devices to supply data to the microprocessor.
• READY signal: used to insert wait states into the bus cycle so that it is
extended by a number of clock periods.
4. Interrupt signals: INTR, INTA
