Queuing Model for the ATM Traffic Simulation

Since the MD1 queuing model assumes infinite buffer space, a single MD1 queue configuration does not experience any cell loss due to lack of buffer space. Every arriving cell is buffered in the queue and eventually processed by the server. By allocating sufficiently large buffer space, i.e., 100 buffers for an 8×8 ATM switch running at 100 Mbps, the infinite buffer space requirement for the MD1 queuing model has been satisfied. Since no cell is lost due to lack of buffer space, the increase in message length has no influence on the throughput. This is clearly shown in Figure 10-8. The single MD1 queuing configuration is expanded to multi-MD1 queue configuration by assigning a MD1 queue for each input-output port pair of an ATM switch. In this configuration each user is assigned to a particular input-output port pair. This configuration is very similar to the Permanent Virtual Circuit PVC concept used in ATM networks. The computer simulation results for this configuration are presented in Figures 10-11 through 10-14. The performance measurements for this configuration are in agreement with the single MD1 configuration. The effects of limited buffer size on switch performance are discussed next. The limited buffer size can significantly influence the performance of the switch in terms of cell loss, throughput and cell delay. In the ATM switching environment, simply increasing the buffer size does not always yield optimal performance. Although an increase in buffer size lowers the cell loss rate, it also increases the cell delay at the same time. This is clearly evident in Figures 10-15, 10-16 and 10-17. Therefore, a proper balance must be established between cell delay, cell loss and throughput performance objectives when determining buffer size for an ATM switch. Figure 10-7 Cell delay for single MD1 queue configuration: fixed message length m and fixed destination address case. Figure 10-8 Throughput for single MD1 queue configuration: fixed message length m and fixed destination address case. Figure 10-9 Mean Queue Length for single MD1 queue configuration: fixed message length m and fixed destination address case. Figure 10-10 Mean Time-in-System for single MD1 queue configuration: fixed message length m and fixed destination address case. Figure 10-11 Cell delay for multiple MD1 queue configuration: fixed message length m and fixed destination address case. Figure 10-12 Throughput for multiple MD1 queue configuration: fixed message length m and fixed destination address case. Figure 10-13 Mean Queue Length for multiple MD1 queue configuration: fixed message length m and fixed destination address case.