Figure 6-5 Bandwidth allocation according to ABR service class.
Previous Table of Contents Next
Copyr ight © CRC Pr ess LLC
by Abhijit S. Pandya; Ercan Sen CRC Press, CRC Press LLC
ISBN: 0849331390 Pub Date: 110198
Previous Table of Contents Next
Chapter 7 Switching Architectures for ATM Networks
An ideal N×N switching architecture for ATM networks can be modeled as a box with N input ports and N output ports, providing connections between its N input ports and N output ports. Figure 7-1
illustrates such an ideal switching model. The internal structure of a switching architecture determines how the connections are made between its input-output pairs. Depending on its internal structure, a
switching architecture can be classified into the following categories:
• blocking or non-blocking • self-routing or central routing
• input buffering, output buffering or central buffering • buffer management: complete sharing, partial sharing, and complete partitioning
Figure 7-1 An ideal ATM switch model.
I. Buffering Models for ATM Switching Networks
Buffering allows smoothing of peak cell traffic through storage of cells to be transmitted at a later time. Buffering in an ATM switch can take one of three basic forms: input buffering, output buffering and
central buffering [Karol 1987, Karol 1988, Kim 1990, Mun 1994, Re 1993]. Input buffering stores incoming cells at the input ports of an ATM switch while output buffering stores cells at the output ports
of an ATM switch. In case of central buffering, a central buffer space is shared by both input and output ports.
A. Input Buffering
With input buffering, the switching network can run at the same speed as the inputoutput port transmission speed. However, the performance of a switching network with input buffering and First-In
First-Out FIFO server strategy suffers considerably due to Head-Of-Line HOL blocking. The maximum throughput attainable with input buffering and FIFO strategy is limited to 0.586 as N becomes
large [Karol 1988].
The performance of input buffering can be improved significantly by changing the server strategy. If we allow the routing mechanism to choose cells for transmission to output ports from each input buffer
within a window of W cells, then it becomes possible to choose a maximum number of cells with disjoint output destinations to be transmitted in a single time slot. In [Karol 1988], it has been shown
that with such a modification, it is possible to increase the performance of input buffering to 0.88. However, the routing for such a scheme is a NP-complete problem and the solution has to be obtained
within one time slot so that while currently selected cells are being transmitted the routing mechanism can select a new set of cells to be transmitted in the next time slot.
B. Output Buffering
Output buffering is superior to input buffering in terms of performance. However, output buffering requires that the switching network has to run N times faster than the inputoutput port transmission
speed in order to be able to handle N packets arriving at the same output port within a single time slot.
