Technology Node
0.5 µm
0.35 µm
0.25 µm
0.18 µm
0.13 µm
90nm 65nm
45nm 30nm
Transistor Physical Gate
Length
130nm 70nm
50nm 30nm
20nm 15nm
1995 2005
1990 2000
2010 0.01
0.10 1.00
Micrometer
Nanotechnology
10 100
1000
Nanometer
Transistor Scaling
•
Transistor physical gate length will reach ~15nm before end of this decade, and ~10nm early next decade
3
R. Chau, Intel, ICSICT 2004
Transistor Scaling and Research Roadmap Transistor Scaling and Research Roadmap
4
Gate
L
G
= 10nm L
G
= 10nm
20nm Length Development
25 nm 15nm
15nm Length 15nm Length
Research Research
65nm Node 2005
45nm Node 2007
90nm Node 2003
32nm Node 2009
22nm Node 2011
10nm Length 10nm Length
Research Research
C C
- -
nanotube nanotube
Prototype Prototype
Research Research
Nanowire Nanowire
Prototype Prototype
Research Research
5 n m 5 n m
5nm
2015-2019 Research
50nm Length Production
30nm Length Development
Drain Source
Source
III-V Device Prototype
Research
S G
D
Epi III-V
Non-planar Tri-Gate Architecture Option
30nm
Uniaxial Strain
SiGe SD PMOS
High-K Metal-Gate
Options
1.2nm Ultra-thin SiO2
Robert Chau, Intel, ICSICT 2004
State-of-the-Art Si Nanotechnologies
•
Gate Dielectric Technology
–
Ultra-thin 1.2 nm nitrided gate oxide implemented
in 90nm technology node
–
New high-Kmetal-gate stack key option for 45nm
node
•
Strained Si Technology
•
Uniaxial strain implemented in 90nm node
•
Biaxial strain
•
Non-planar Tri-gate Transistor Architecture
option for 45nm, 32nm node and beyond
•
Si transistor is becoming less silicon
–
SiGe SD, metal gate electrodes, metallic high-K etc
5
R. Chau, Intel, ICSICT 2004
High-KPolySi Transistors
1.E-08 1.E-07
1.E-06 1.E-05
1.E-04 1.E-03
1.E-02
0.2 0.4
0.6 0.8
1 1.2
Vg V Id
A µ
m
Vd = 1.3V Lg = 110nm
PolySiHigh-K Toxe = 17A
PolySiSiO2 Toxe = 20A
•
High-KpolySi transistors suffer from high V
TH
, degraded channel mobility and poor drive performance
High-K Poly-Si 100
200 300
400 500
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Electric Field MVcm
In versio
n Electro
n Mo
bility cm2Vs
Universal Mobility
SiO2Poly-Si
6
R. Chau, Intel, ICSICT 2004
High-K and PolySi are Incompatible
O M
O O
O O
M M
M O
M O
O O
O M
M M
O O
O O
O O
O O
O M
O O
O O
M M
M O
M O
O O
O M
M M
M
O M
O O
O O
M M
M O
M O
O O
O M
M M
M Si
Si Si
Si Si
Si Si
Si Si
Si Si Si Si Si Si Si Si Si Si
Si Si
Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si
Si
M Si
Si Si
Si Si
Poly Si
Interface
High-K
M = Zr, Hf
Defect
•
Defect formation at the polySi-high-K interface
•
1 defect out of 100 surface atoms to pin Vth
7
Robert Chau, Intel, ICSICT 2004
Phonon Scattering Limits Channel
Mobility in High-KPolySi Transistors
1.0E-05 1.5E-05
2.0E-05 2.5E-05
3.0E-05 3.5E-05
4.0E-05 4.5E-05
0.1 0.3
0.5 0.7
0.9 1.1
1.3 1.5
E-Field MVcm d1ueffdT
High-KPolySi
SiO2PolySi
Phonon scattering
E-Field
µ
1 ∂
∂ T
PH
µ 1
∂ ∂
T
Coul
µ
1 =
∂ ∂
T
SR
µ
µ
ph
↓ T ↑
µ
Coul
↑ T ↑ µ
SR
~ const
Coulombic Phonon Surface
Roughness
SR ph
Coul eff
µ µ
µ µ
1 1
1 1
+ +
=
8
Robert Chau, Intel, ICSICT 2004
Metal Gate Screens Surface Phonon Scattering and Improves Mobility in High-K Transistors
200 400
600 800
1000 1200
0.5 1
1.5 Transverse Electric Field, E
eff
MVcm Surface Phonon Limited Mobility
cm
2
V.s
471 P860
W019-BKM
SiO2 + Poly-Si HfO2 + PolySi
HfO2+Metal Gate
T = 25 C
High-KPolySi SiO2PolySi
High-KMetal-gate
9
R. Chau, Intel, ICSICT 2004
