Robert Chau ICSICT 101904

(1)

Advanced CMOS Transistors

in the Nanotechnology Era

for High-Performance, Low-Power

Logic Applications

Robert Chau

Intel Fellow

Director of Transistor Research

and Nanotechnology

Intel Corporation

Oct 19, 2004

(2)

Content

• Introduction

• State-of-the-art Si nanotechnologies for

advanced CMOS transistors

–

High-K, Metal-gate, Strain, Non-planar Tri-gate

• Emerging nano-electronic materials and

devices

for future logic applications

–

III-V, Carbon Nanotubes, Semiconductor

Nanowires

• Challenges and Opportunities

• Summary

(3)

Technology Node

0.5µm

0.35µm

0.25µm

0.18µm

0.13µm 90nm

65nm

45nm 30nm

Transistor Physical Gate

Length 130nm

70nm

50nm

30nm

20nm

15nm

1995

2005

1990

2000

2010

0.01

0.10

1.00 Micrometer

Nanotechnology

10

100 1000

Nanometer

Transistor Scaling

• Transistor physical gate length will reach ~15nm before

end of this decade, and ~10nm early next decade

(4)

Transistor Scaling and Research Roadmap

Gate

LG= 10nm

20nm Length (Development) 25 nm 15nm 15nm Length 15nm Length (Research) (Research) 65nm Node 2005 45nm Node 2007 90nm Node 2003 32nm Node

2009 22nm Node

2011 10nm Length 10nm Length (Research) (Research) C

C--nanotubenanotube Prototype

Prototype

(Research)

(Research) NanowireNanowire

Prototype

(Research)

5 n m

5nm

2015-2019

Research

50nm Length (Production) 30nm Length (Development)

Drain

Source

III-V Device Prototype (Research)

S G _D

Epi III-V Non-planar Tri-Gate Architecture Option 30nm Uniaxial Strain

SiGe S/D PMOS

High-K & Metal-Gate Options

1.2nm Ultra-thin SiO2

(5)

State-of-the-Art Si Nanotechnologies

• Gate Dielectric Technology

– Ultra-thin 1.2 nm nitrided gate oxide (implemented

in 90nm technology node)

– New high-K/metal-gate stack (key option for 45nm

node)

• Strained Si Technology

• Uniaxial strain (implemented in 90nm node) • Biaxial strain

• Non-planar Tri-gate Transistor Architecture

(

option for 45nm, 32nm node and beyond)

• Si transistor is becoming less silicon

– SiGe S/D, metal gate electrodes, metallic high-K etc 5

(6)

High-K/PolySi Transistors

1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02

0 0.2 0.4 0.6 0.8 1 1.2 Vg (V)

(

/µ

Vd = 1.3V Lg = 110nm

PolySi/High-K Toxe = 17A

PolySi/SiO2 Toxe = 20A

•

High-K/polySi transistors suffer from high V_TH,

degraded channel mobility and poor drive performance

High-K / Poly-Si

100 200 300 400 500

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Electric Field (MV/cm)

versio

Electro

bility

(cm2/Vs)

Universal Mobility

SiO2/Poly-Si

(7)

High-K and PolySi are Incompatible

O M

O O O O

M M M

O M

O O O O

M M M

O O O O O O O O

O M

O O O O

M M M

O M

O O O O

M M M

O M

O O O O

M M M

O M

O O O O

M M M

M Si

Si Si Si Si Si Si

Si Si

Si Si Si Si Si Si Si Si Si Si

M Si Si Si Si Si

Poly Si

Interface

High-K

M = Zr, Hf

Defect

• Defect formation at the polySi-high-K interface

• 1 defect out of 100 surface atoms to pin Vth

(8)

Phonon Scattering Limits Channel

Mobility in High-K/PolySi Transistors

1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 4.0E-05 4.5E-05

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5

E-Field (MV/cm) d(1/ueff)/dT High-K/PolySi SiO2/PolySi Phonon scattering E-Field µ 0 1 > ∂ ∂ T PH µ 0 1 < ∂ ∂ T Coul µ 0 1 = ∂ ∂ T SR µ

µ_ph ↓ T ↑

µ_Coul ↑ T ↑

µ_SR~ const

Coulombic Phonon _Surface

Roughness

SR ph

Coul

eff µ µ µ

1 1

1 ₌ ₊ ₊

(9)

Metal Gate Screens Surface Phonon Scattering

and Improves Mobility in High-K Transistors

0 200 400 600 800 1000 1200

0 0.5 1 1.5

Transverse Electric Field, Eeff ( MV/cm)

Surface Phonon Limited Mobility

(cm

2 /V.s)

471

P860

W019-BKM

SiO2 + Poly-Si HfO2 + PolySi HfO2+Metal Gate

T = 25 C

High-K/PolySi SiO2/PolySi

High-K/Metal-gate

(10)

Metal Gate Electrodes with the “Right” Work

Functions are Required for Correct Transistor V

_TH

NDK

SDK

-1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1

N+poly P+pol

P-metal

N-metal Metal A Metal B Metal C Metal D Metal E Metal F Metal G Metal H Metal I Metal J Gate Electrode Materials

Transistor Flatband

Voltage

(V)

P-type Metal on High-K

N-type Metal on High-K

N+ PolySi/SiO2

P+ PolySi/SiO2

Mid-gap Metal on High-K

(11)

High-Performance High-K/Metal-Gate CMOS

Transistors

(Thin Toxe, Correct V

_TH

, High Mobility

and Low Gate Leakage)

1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02

-1.4 -1 -0.6 -0.2 0.2 0.6 1 1.4

GATE VOLTAGE (V)

IN CUR

ENT (A

/µ

NMOS PMOS

L_g= 80 nm

T_oxe= 14.5 Å

|V_ds| = 0.05, 1.3 V

1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02

-1.4 -1 -0.6 -0.2 0.2 0.6 1 1.4

GATE VOLTAGE (V)

IN CUR

ENT (A

/µ

NMOS PMOS

L_g= 80 nm

T_oxe= 14.5 Å

|V_ds| = 0.05, 1.3 V

0.0E+00 2.0E-04 4.0E-04 6.0E-04 8.0E-04 1.0E-03 1.2E-03 1.4E-03 1.6E-03 1.8E-03

-1.4 -1 -0.6 -0.2 0.2 0.6 1 1.4 Vds (V) Id ( A /µ m ) NMOS PMOS

Lg = 80nm Toxe, inv = 14.5Å |Vgs|= 0V to 1.3V

•

High-K/Metal-K is a key option for the 45nm node

(12)

Channel Mobility Enhancement using

Uniaxial Strain (Implemented in 90nm node)

SiGe

PMOS

Uniaxial, Compressive Strain in Si Channel in PMOS using SiGe S/D

Uniaxial, Tensile Strain in Si

Channel in NMOS using Silicon Nitride Cap

NMOS

High Tensile Silicon Nitride Film

(13)

Channel Mobility Enhancement Using

Biaxial Strain (PMOS Example)

Strained SiGe channel

TiN / High-K gate stack

Strained SiGe channel

TiN / High-K gate stack

Strained SiGe channel

TiN / High-K gate stack High-K/Metal-Gate Stack

Strained SiGe Channel

Silicon Substrate

■ ● ◆

High-K/MG on SiGe(30% Ge) High-K/MG on SiGe(25% Ge) High-K/MG on SiGe(20% Ge) High-K/MG on Si

SiO2 Universal Mobility

Si Strained SiGe (Biaxial

Compressive)

Si SiGe

• Enhancement in both

low-field and high-field

channel mobility

(14)

W _Si

T_Si L_G

W _Si

T_Si L_G

Non-Planar Transistors

T_Si L_G

W _Si

T_Si L_G

W _Si

ISOLATION

Double Gate (e.g. FINFET) Non-Planar Tri-Gate

(15)

Non-Planar Tri-Gate Transistor

Si Planar

Si Non-planar Tri-gate

NMOS

Si Planar

NMOS

Si Tri-gate

•

Si planar transistors becoming difficult to scale

•

Tri-gate architecture improves electrostatics significantly and extends transistor scalability

•

Tri-gate is a key device option for 32nm node and beyond

(16)

Tri-Gate Transistor Architecture for

32nm Node and Beyond

PMOS

Si Planar

Si Non-planar Tri-gate

PMOS

Si Planar

Si Non-planar Tri-gate

•

Tri-gate architecture shows significantly improved device electrostatics and short-channel performance over

conventional planar architecture

(17)

Nanotechnology Research

L_g = 10 nm

(a)

L_g = 10 nm _Gate

Source Si body Drain Gate Source Drain Source CNT Single -wall D = 1.4 nm

Gate (Pt) Drain

(Pd)

L_g = 75 nm

(d)

Source

CNT

Single -wall D = 1.4 nm

Gate (Pt) Drain

(Pd)

L_g = 75 nm

(d)

Source

CNT

Single -wall D = 1.4 nm

Gate (Pt) Drain

(Pd)

L_g = 75 nm

III-V Gate Drain Source Source (c) Multi epitaxial layers Gate Drain Source Source (c) Multi epitaxial layers Gate Drain Source Source Multi epitaxial III-V layers

5 nm 5 nm

2.0 nm High-K Gate

5.0 nm Si Nanowire

5 nm 5 nm

2.0 nm High-K Gate

5.0 nm Si Nanowire

• Semiconductor

Nanowires

(Si, SiGe, Ge etc)

• Carbon Nanotube • III-V Transistors

(18)

Intrinsic gate delay CV/I for PMOS

0.1 1 10 100 1000

1 10 100 1000 10000

GATE LENGTH [nm]

]

Si MOSFETs CNTFETs Si Nanowires PMOS

• CNT shows significant p-ch CV/I improvement over Si

– CNT has >20X higher effective p-ch mobility than Si

• Si nanowires do not show improvement over Si

(19)

• n-channel CNT not as well established as p-channel CNT

• III-V (e.g. InSb) devices show significant CV/I improvement over Si

– III-V devices have >50X higher effective n-ch mobility than Si

– III-V devices operated at low V_CC= 0.5V

• Scalability of III-V devices to shorter Lg remains to be demonstrated

Intrinsic gate delay CV/I for NMOS

(20)

III-V Transistors for Low Vcc

GATE DRAIN DRAIN SOURCE III-V 0 20 40 60 80 100 120 140 160 180

1 10 100 1000

Power Dissipation (mW/mm)

Cutoff Frequency, fT (GHz)

InSb Vds=0.3V InSb Vds=0.5V InSb Vds=0.6V InSb Vds=0.7V Si Vds=0.5V Si Vds=0.7V Si Vds=1V Si Vds=1.2V III-V FETs (Lg~200nm) Si FETs (Lg~80nm) 5-10X Lower Power Dissipation 0.5V 1.2V

Robert Chau, Intel, ICSICT 2004

0.3V

T eff

v

f

L

g

WL

C

I

WLV

C

I

CV

π

2

1 =

(21)

Device Evolution and Process Challenge

Planar Si

Source Drain

Gate

Tri-gate

CNT/Nanowire

GATE DRAIN

DRAIN SOURCE

Epitaxial III-V

III-V

Bottom-up Approach

•

Chirality issues

•

Positioning issues

(required >10 billion gates)

32nm Node (2009)

Conventional Processing (being done in 300mm Fabs)

•

Top-down Approach – std litho and etch

•

Integration with Si?

(22)

Summary

• Through Si breakthroughs and innovations,

Si CMOS transistor scaling will continue

through middle of next decade

• Future logic transistor scaling and

performance require research on new

device structures, new materials, new

process technologies, and new integration

schemes

• Emerging nanoelectronic devices show

both challenges and opportunities for

future logic transistor applications

(1)

Nanotechnology Research

L_g = 10 nm (a)

L_g = 10 nm _Gate

Source Si body Drain Gate Source Drain Source CNT Single -wall D = 1.4 nm

Gate (Pt) Drain

(Pd)

L_g = 75 nm

(d)

Source

CNT

Single -wall D = 1.4 nm

Gate (Pt) Drain

(Pd)

L_g = 75 nm

(d)

Source

CNT

Single -wall D = 1.4 nm

Gate (Pt) Drain

(Pd)

L_g = 75 nm

5 nm

2.0 nm High-K Gate

5.0 nm Si Nanowire

5 nm

2.0 nm High-K Gate

5.0 nm Si Nanowire

• Semiconductor

Nanowires

(Si, SiGe, Ge etc)

(2)

Intrinsic gate delay CV/I for PMOS

0.1 1 10 100 1000

1 10 100 1000 10000

GATE LENGTH [nm]

]

Si MOSFETs CNTFETs Si Nanowires

PMOS

• CNT shows significant p-ch CV/I improvement over Si

– CNT has >20X higher effective p-ch mobility than Si

(3)

• n-channel CNT not as well established as p-channel CNT

• III-V (e.g. InSb) devices show significant CV/I improvement over Si – III-V devices have >50X higher effective n-ch mobility than Si

– III-V devices operated at low V_CC= 0.5V

• Scalability of III-V devices to shorter Lg remains to be demonstrated

(4)

III-V Transistors for Low Vcc

GATE DRAIN DRAIN SOURCE III-V 0 20 40 60 80 100 120 140 160 180

1 10 100 1000

Power Dissipation (mW/mm)

Cutoff Frequency, fT (GHz)

m v f

L g WL C I WLV C I CV π 2 1 0

0 = = =

(5)

Device Evolution and Process Challenge

Planar Si

Source Drain Gate

Tri-gate

CNT/Nanowire

GATE DRAIN

DRAIN SOURCE

Epitaxial III-V

III-V

Bottom-up Approach

• Chirality issues

• Positioning issues

(required >10 billion gates)

32nm Node (2009)

Conventional Processing (being done in 300mm Fabs)

• Top-down Approach – std litho and etch

(6)

Summary

• Through Si breakthroughs and innovations,

Si CMOS transistor scaling will continue through middle of next decade

• Future logic transistor scaling and

performance require research on new device structures, new materials, new

process technologies, and new integration schemes

• Emerging nanoelectronic devices show

both challenges and opportunities for future logic transistor applications