SIMULATOR MODEL – PICmicro MCUs

12.3 SIMULATOR MODEL – PICmicro MCUs

PICmicro MCU's use Harvard architecture (separate program and data memory) as opposed to Von Neumann architecture (combined program and data memory.) Therefore, program memory instructions are not limited to 8-bit data lengths. Program memory, or core, instruction length is used to group PICmicro MCU's.

At the time this documentation was produced, the following cores are associated with the listed devices:

• 12-Bit Core Device Model – PIC12C5XX, PIC12CE5XX, PIC16X5X, PIC16C505 • 14-Bit Core Device Model – PIC12C67X, PIC12CE67X, PIC12F629/675, PIC16 • 16-Bit Core Device Model – PIC17 • 16-Bit Core Device Model – PIC18

The 12-bit, 14-bit and 16-bit (PIC17) core devices have word-addressed program memory space.

The 16-bit (PIC18) core devices have a byte-organized program memory space. There are some restrictions in the silicon on how the program memory space can be accessed, especially when using long writes to program memory. The simulator may not show the same restrictions in all situations. Consult the data sheet for proper operation.

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MPLAB ® IDE User’s Guide

12.3.1 12-Bit Core Device Model – PIC12C5XX, PIC12CE5XX, PIC16X5X, PIC16C505

The following topics discuss the 12-bit core device features modeled in the simulator. • 12-Bit Core I/O Pins

• 12-Bit Core CPU • 12-Bit Core Peripherals

12.3.1.1 12-BIT CORE I/O PINS The 12-bit core devices have I/O pins multiplexed with other peripherals (and therefore

referred by more than one name). MPLAB SIM recognizes only the following pin names as valid I/O pins:

Note: Pins are only available as described in the data sheet of the specific device. • MCLR

• T0CKI • GP0-GP5 • RA0-RA3 • RB0-RB7 • RC0-RC7 • RD0-RD7 • RE4-RE7

12.3.1.2 12-BIT CORE CPU

Reset Conditions All reset conditions are supported by the MPLAB SIM simulator.

The Time-out (TO) and Power-down (PD) bits in the STATUS register reflect appropri- ate reset condition. This feature is useful for simulating various power-up and time-out forks in your code.

A MCLR reset during normal operation can easily be simulated by driving the MCLR pin low (and then high) via stimulus or by selecting Debugger>Reset>MCLR Reset.

Watchdog Timer The Watchdog Timer is fully simulated in the MPLAB SIM simulator.

The period of the WDT is determined by the pre/postscaler settings in the OPTION_REG register. The basic period (with pre/postscaler at 1:1) is approximated, to the closest instruction cycle multiple, in the device data sheet.

In the Configuration Bits dialog (Configuration>Configuration Bits) you enable/disable the WDT and set the pre/postscaler.

A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and WDT actually overflows. On WDT time-out, the simulator will halt or reset, depending on the selection in the Break Options tab of the Settings dialog.

12.3.1.3 12-BIT CORE PERIPHERALS Along with core support, MPLAB SIM fully supports the TIMER0 timer/counter module

in both internal and external clock modes. It is important to remember that, because MPLAB SIM executes on instruction cycle

boundaries, resolutions below 1 T CY cannot be simulated.

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Simulator Overview

12.3.2 14-Bit Core Device Model – PIC12C67X, PIC12CE67X, PIC12F629/675, PIC16

The following topics discuss the 14-bit core device features modeled in the simulator. • 14-Bit Core I/O Pins

• 14-Bit Core Interrupts • 14-Bit Core CPU • 14-Bit Core Peripherals

12.3.2.1 14-BIT CORE I/O PINS The 14-bit core devices have I/O pins multiplexed with other peripherals (and therefore

referred by more than one name). MPLAB SIM recognizes only the following pin names as valid I/O pins:

Note: Pins are only available as described in the data sheet of the specific device. • MCLR

• GP0-GP5 • RA0-RA5 • RB0-RB7 • RC0-RC7 • RD0-RD7 • RE0-RE7

12.3.2.2 14-BIT CORE INTERRUPTS The following interrupts are supported:

• Timer0 overflow • Timer1 overflow • Timer2 • CCP1 • CCP2 • Change on Port RB <7:4> • External interrupt from RB0/INT pin • Comparators • A/D complete • EEPROM write complete

12.3.2.3 14-BIT CORE CPU

Reset Conditions All reset conditions are supported by the MPLAB SIM simulator.

The Time-out (TO) and Power-down (PD) bits in the STATUS register reflect appropri- ate reset condition. This feature is useful for simulating various power-up and time-out

forks in the user code.

A MCLR reset during normal operation or during Sleep can easily be simulated by driving the MCLR pin low (and then high) via stimulus or by selecting Debugger> Reset>MCLR Reset.

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MPLAB ® IDE User’s Guide

Sleep When executing a Sleep instruction, MPLAB SIM will appear “asleep” until a wake-up

from sleep condition occurs. For example, if the Watchdog Timer has been enabled, it will wake the processor up from sleep when it times out (depending upon the pre/postscaler setting).

An example of a wake-up-from-sleep condition would be Timer1 wake up from sleep. In this case, when the processor is asleep, Timer1 would continue to increment until it overflows. If the interrupt is enabled, the timer will wake the processor on overflow and branch to the interrupt vector.

Watchdog Timer The Watchdog Timer is fully simulated in the MPLAB SIM simulator.

The period of the WDT is determined by the pre/postscaler settings in the OPTION_REG register. The basic period (with pre/postscaler at 1:1) is approximated, to the closest instruction cycle multiple, in the device data sheet.

In the Configuration Bits dialog (Configuration>Configuration Bits) you enable/disable the WDT and set the pre/postscaler.

A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and WDT actually overflows. On WDT time-out, the simulator will halt or reset, depending on the selection in the Break Options tab of the Settings dialog.

12.3.2.4 14-BIT CORE PERIPHERALS Along with core support, MPLAB SIM supports the following peripheral modules, in

addition to general purpose I/O. Consult the data sheet for the particular device you are using for information on which symbols are implemented.

Note: Even if peripheral functionality is not supported in the simulator, the

peripheral registers will be available as read/write.

• Timers • CCP/ECCP • Comparators (Limited) • A/D Converter (Limited) • USART • EEPROM Data Memory

The delays are implemented on all peripherals, but the interrupt latency is not. Timers

Timer0 (and the interrupt it can generate on overflow) is fully supported, and will incre- ment by the internal or external clock. Clock input must have a minimum high time of 1 T CY and a minimum low time of 1 T CY due to stimulus requirements.

Timer1 in its various modes is supported, except when running in counter mode by an external crystal. MPLAB SIM supports Timer1 interrupts generated on overflow, and

interrupts generated by wake-up from sleep. The external oscillator on RC0/RC1 is not simulated, but a clock stimulus can be assigned to those pins.

Timer2 and the interrupt that can be generated on overflow are fully supported.

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Simulator Overview

CCP/ECCP Capture

MPLAB SIM fully supports capture and the interrupt generated. Compare MPLAB SIM supports compare mode, its interrupt and the special event trigger

(resetting Timer1 by CCP1). PWM PWM output is supported (resolution greater than 1 T CY only).

Comparators (Limited) Only comparator modes that do not use Vref are simulated in MPLAB SIM.

A/D Converter (Limited) All the registers, timing function and interrupt generation are implemented. The

simulator, however, does not load any meaningful value into A/D result register (ADRES) at the end of a conversion.

Note: If you have trouble with I/O pins on processors that have A/D (PIC16C74, PIC16F877, etc.), make certain that the ADCON registers are configuring those pins for digital I/O rather than for analog input. For most processors, these default to analog inputs and the associated pins cannot be used for I/O until the ADCON (or ADCON1) register is set properly.

USART USART functionality is supported.

EEPROM Data Memory The EEPROM data memory is fully simulated. The registers and the read/write cycles

are fully implemented. The write cycle time is approximated to 10 ms (to nearest instruction cycle multiple).

The simulator simulates the functions of WRERR and WREN control bits in the EECON1 register.

12.3.3 16-Bit Core Device Model – PIC17

The following topics discuss the 16-bit core device features modeled in the simulator. • 16-Bit Core (PIC17) I/O Pins

• 16-Bit Core (PIC17) Interrupts • 16-Bit Core (PIC17) CPU • 16-Bit Core (PIC17) Processor Modes • 16-Bit Core (PIC17) Peripherals

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12.3.3.1 16-BIT CORE (PIC17) I/O PINS PIC17 devices have I/O pins multiplexed with other peripherals and therefore referred

by more than one name. MPLAB SIM recognizes only the following pin names as valid I/O pins:

Note: Pins are only available as described in the data sheet of the specific device. • MCLR

• RA0-RA5 • RB0-RB7 • RC0-RC7 • RD0-RD7 • RE0-RE2

12.3.3.2 16-BIT CORE (PIC17) INTERRUPTS The following interrupts are supported:

• External interrupt on INT pin • TMR0 overflow interrupt • External interrupt on RA0 pin • Port B input change interrupt • Timer/Counter1 interrupt • Timer/Counter2 interrupt • Timer/Counter3 interrupt • Capture1 interrupt • Capture2 Interrupt

12.3.3.3 16-BIT CORE (PIC17) CPU

Reset Conditions All reset conditions are supported by the MPLAB SIM simulator.

The Time out (TO) and Power-Down (PD) bits in the CPUSTA register reflect appropri- ate reset condition. This feature is useful for simulating various power-up and time-out forks in the user code.

A MCLR reset during normal operation or during Sleep can easily be simulated by driving the MCLR pin low (and then high) via stimulus.

Sleep When executing a Sleep instruction, MPLAB SIM will appear “asleep” until a wake-up

from sleep condition occurs. For example, if the Watchdog Timer has been enabled, it will wake the processor up from sleep when it times out (depending upon the postscaler setting).

An example of a wake-up-from-sleep condition would be an input change on Port B. If the interrupt is enabled and the GLINTD bit is set, the processor will wake up and will

resume executing from the instruction following the Sleep command. If the GLINTD = 0, the normal interrupt response will take place.

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Simulator Overview

Watchdog Timer The Watchdog Timer is fully simulated in the MPLAB SIM simulator.

The period of the WDT is determined by the postscaler configuration bits WDTPS0:1. The basic period (with postscaler at 1:1) is approximated, to the closest instruction cycle multiple, in the device data sheet. Setting the configuration bits WDTPS0:1 to 00 will disable the WDT.

In the Configuration Bits dialog (Configuration>Configuration Bits) you enable/disable the WDT and set the postscaler.

A WDT time-out is simulated when WDT is enabled, proper postscaler is set and WDT actually overflows. On WDT time-out, the simulator will halt or reset, depending on the selection in the Break Options tab of the Settings dialog.

12.3.3.4 16-BIT CORE (PIC17) PROCESSOR MODES The following processor modes are supported by MPLAB SIM for devices which allow

them: • Microcontroller (Default)

• Microprocessor • Microprocessor w/Boot • Extended Microcontroller

Set the processor mode in code ( __config) or the Configuration Bits dialog.

12.3.3.5 16-BIT CORE (PIC17) PERIPHERALS Along with providing core support, MPLAB SIM supports the following peripheral

modules, in addition to general purpose I/O: • Timer0

• Timer1 and Timer2 • Timer3 and Capture • PWM

The delays are implemented on all peripherals, but the interrupt latency is not. Timer0

Timer0 and the interrupt it can generate on overflow is fully supported, and will increment by the internal or external clock. Delay from external clock edge to timer increment has also been simulated, as well as the interrupt latency period. Clock input must have a minimum high time of 1 T CY and a minimum low time of 1 T CY due to the stimulus file requirements.

Timer1 and Timer2 Timer1 and Timer2 in its various modes is fully supported. Delays from clock edge to

increment (when configured to increment from rising or falling edge of external clock) is simulated as well as the interrupt latency periods. Clock input must have a minimum high time of 1 T CY and a minimum low time of 1 T CY due to the stimulus file requirements.

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Timer3 and Capture The MPLAB simulator fully supports Timer3 and the Capture module in all of its modes.

Delays from clock edge to increment (when configured in external mode), delay for capture and interrupt latency periods are fully supported. Clock input must have a minimum high time of 1 T CY and a minimum low time of 1 T CY due to the stimulus file requirements.

PWM Both PWM outputs are supported (resolution greater than 1 T CY only).

12.3.4 16-Bit Core Device Model – PIC18

The following topics discuss the enhanced 16-bit core device features modeled in the simulator.

• 16-Bit Core (PIC18) I/O Pins • 16-Bit Core (PIC18) Interrupts • 16-Bit Core (PIC18) CPU • 16-Bit Core (PIC18) Peripherals

12.3.4.1 16-BIT CORE (PIC18) I/O PINS PIC18 devices have I/O pins multiplexed with other peripherals (and therefore referred

by more than one name). MPLAB SIM recognizes only the following pin names as valid I/O pins:

Note: Pins are only available as described in the data sheet of the specific device. • MCLR

• RA0-RA5 • RB0-RB7 • RC0-RC7 • RD0-RD7 • RE0-RE2

12.3.4.2 16-BIT CORE (PIC18) INTERRUPTS The following interrupts are supported:

• External interrupt on INT pin • TMR0 overflow interrupt • External interrupt on RA0 pin • Port B input change interrupt • Timer/Counter1 interrupt • Timer/Counter2 interrupt • Timer/Counter3 interrupt • Capture1 interrupt • Capture2 Interrupt

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Simulator Overview

12.3.4.3 16-BIT CORE (PIC18) CPU

Reset Conditions All reset conditions are supported by the MPLAB SIM simulator.

The Time out (TO) and Power-Down (PD) bits in the RCON register reflect appropriate reset condition. This feature is useful for simulating various power-up and time-out forks in the user code.

You cannot reset by toggling MCLR using stimulus control. You must use Debugger> Reset>MCLR Reset.

Sleep When executing a Sleep instruction, MPLAB SIM will appear “asleep” until a wake-up

from sleep condition occurs. For example, if the Watchdog Timer has been enabled, it will wake the processor up from sleep when it times out (depending upon the pre/postscaler setting).

An example of a wake-up-from-sleep condition would be an input change on Port B. If the interrupt is enabled and the GLINTD bit is set, the processor will wake up and will resume executing from the instruction following the Sleep command. If the GLINTD =

0, the normal interrupt response will take place.

Watchdog Timer The Watchdog Timer is fully simulated in the MPLAB SIM simulator.

The period of the WDT is determined by the pre/postscaler configuration bits WDTPS0:2. The basic period (with pre/postscaler at 1:1) is approximated, to the closest instruction cycle multiple, in the device data sheet.

Setting the configuration bit WDTEN to 0 will disable the WDT, unless it is enabled by the SWDTEN bit of the WDTCON register. Setting the configuration bit WDTEN to 1 will enable the WDT regardless of the value of the SWDTEN bit.

In the Configuration Bits dialog (Configuration>Configuration Bits) you enable/disable the WDT and set the pre/postscaler.

A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and WDT actually overflows. On WDT time-out, the simulator will halt or reset, depending on the selection in the Break Options tab of the Settings dialog.

12.3.4.4 16-BIT CORE (PIC18) PERIPHERALS Along with core support, MPLAB SIM supports the following peripheral modules, in

addition to general-purpose I/O: • Timers

• CCP/ECCP • Comparators (Limited) • A/D Converter (Limited) • USART • EEPROM Data Memory The delays are implemented on all peripherals, but the interrupt latency is not.

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Timers Timer0 (and the interrupt it can generate on overflow) is fully supported, and will

increment by the internal or external clock. Clock input must have a minimum high time of 1 T CY and a minimum low time of 1 T CY due to stimulus requirements.

All Other Timers in their various modes are supported, except for modes using an external crystal. MPLAB SIM supports Timer interrupts generated on overflow, and interrupts generated by wake-up from sleep. Although the external oscillator is not simulated, a clock stimulus can be assigned to those pins.

CCP/ECCP Capture

MPLAB SIM fully supports capture and the interrupt generated. Compare MPLAB SIM supports compare mode, its interrupt and the special event trigger

(resetting a Timer by CCP). PWM PWM output is supported (resolution greater than 1 T CY only).

Comparators (Limited) Only comparator modes that do not use Vref are simulated in MPLAB SIM.

A/D Converter (Limited) All the registers, timing function and interrupt generation are implemented. The

simulator, however, does not load any meaningful value into A/D result register (ADRES) at the end of a conversion.

Note: If you have trouble with I/O pins on processors that have A/D (PIC16C74, PIC16F877, etc.), make certain that the ADCON registers are configuring those pins for digital I/O rather than for analog input. For most processors, these default to analog inputs and the associated pins cannot be used for I/O until the ADCON (or ADCON1) register is set properly.

USART USART functionality is supported.

EEPROM Data Memory The EEPROM data memory is fully simulated. The registers and the read/write cycles

are fully implemented. The write cycle time is approximated to 10 ms (to nearest instruction cycle multiple).

The simulator simulates the functions of WRERR and WREN control bits in the EECON1 register.

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Simulator Overview