SIMULATOR MODEL – dsPIC DSCs
12.4 SIMULATOR MODEL – dsPIC DSCs
The dsPIC digital signal controller (DSC) is a combination of a digital signal processing (DSP) core and PICmicro microcontroller (MCU) peripheral features. DSCs use a modified Harvard architecture to provide separate program memory and 16-bit data memory spaces.
The following topics discuss the dsPIC device features modeled in the simulator. • I/O Pins
• Exceptions (Traps/Interrupts) • System Integration Block • Memory • Peripherals
12.4.1 I/O Pins
The dsPIC devices have I/O pins multiplexed with other peripherals (and therefore referred by more than one name). The simulator recognizes only the pin names spec- ified in the standard device headers as valid I/O pins. Therefore, you should refer to the header file for your device ( pDeviceNumber.inc) to determine the correct pin names.
12.4.2 Exceptions (Traps/Interrupts)
The simulator supports all core and peripheral traps and interrupts, even if the peripheral is currently not supported.
The dsPIC core features a vectored exception processing structure for up to 8 traps and 54 interrupts or 62 total independent vectors. Each interrupt is prioritized, based on a user-assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest). If a conflict occurs (two interrupts at the same priority), interrupt service will
be based on a predetermined 'natural order' which is hardware-based.
12.4.3 System Integration Block Reset Sources
All reset sources are supported by the MPLAB SIM simulator. Status bits from the RCON register are set or cleared differently in different Reset
situations, as indicated in device data sheet. These bits are used in software to determine the nature of the Reset.
A MCLR reset during normal operation or during Sleep/Idle can easily be simulated by driving the MCLR pin low (and then high) via stimulus or by selecting Debugger> Reset>MCLR Reset.
Sleep/Idle When executing a PWRSAV instruction, MPLAB SIM will appear “asleep” or “idle” until
a wake-up condition occurs. For example, if the Watchdog Timer has been enabled, it will wake the processor up from sleep when it times out (depending upon the
pre/postscaler setting). An example of a wake-up-from-sleep condition would be Timer1 wake up from sleep.
In this case, when the processor is asleep, Timer1 would continue to increment until it matches the period counter. If the interrupt is enabled, the timer will wake the processor and branch to the interrupt vector.
2005 Microchip Technology Inc.
DS51519A-page 177
MPLAB ® IDE User’s Guide
Watchdog Timer The Watchdog Timer is fully simulated in the MPLAB SIM simulator.
The Watchdog Timer can be “Enabled” or “Disabled” through a configuration bit (FWDTEN) in the Configuration register FWDT. Setting FWDTEN = 1 enables the Watchdog Timer. Setting FWDTEN = 0 allows user software to enable/ disable the Watchdog Timer via the SWDTEN (RCON<5>) control bit.
The period of the WDT is determined by the pre/postscaler settings in the FWDT register. The basic period (with pre/postscaler at 1:1) is approximated, to the closest instruction cycle multiple, in the device data sheet.
In the Configuration Bits dialog (Configuration>Configuration Bits) you enable/disable the WDT and set the pre/postscalers.
A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and WDT actually overflows. On WDT time-out, the simulator will halt or reset, depending on the selection in the Break Options tab of the Settings dialog.
12.4.4 Memory
dsPIC device memory – program flash and data RAM – is simulated except for features dependent on security aspects. I.e., protected memory is not simulated.
12.4.5 Peripherals
MPLAB SIM supports all peripheral modules, with functional exceptions listed in the limitations.
The delays are implemented on all peripherals, but the interrupt latency is not.