prep2002_new.ppt 207KB Jun 23 2011 12:30:50 PM

09/14/17 1 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

High-Level Synthesis

High-Level Synthesis

for On-line Testability

for On-line Testability

P. Oikonomakos and M. Zwolinski

P. Oikonomakos and M. Zwolinski

Department of Electronics and

Department of Electronics and

Computer Science,

Computer Science,

University of Southampton

University of Southampton

Hampshire SO17 1BJ

Hampshire SO17 1BJ

UK

09/14/17 2 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

On-line testing

On-line testing

• flight/space electronics_{flight/space electronics}

• industrial/automotive electronics_{industrial/automotive electronics} • medical electronics_{medical electronics}

• deep submicron technologies_{deep submicron technologies}

 _{targets physical system failurestargets physical system failures}  _{detects them while system is detects them while system is}

operating

operating

 _{increases reliability in several increases reliability in several} safety-critical applications,

safety-critical applications,

especially in hostile environments,

especially in hostile environments,

e.g.

09/14/17 3 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

High-level synthesis

High-level synthesis

 _{the designer provides an abstract the designer provides an abstract}

specification of the

specification of the behaviour of his behaviour of his

conceptual design along with his

conceptual design along with his

constraints and requirements

constraints and requirements

 _{the synthesis tool is responsible for the synthesis tool is responsible for} producing an equivalent

producing an equivalent structural structural description

description

 _{high-level synthesis offers :high-level synthesis offers :}

• fast time-to-market_{fast time-to-market}

• fast and efficient design space _{fast and efficient design space}

exploration

exploration

• efficient design optimisation at the _{efficient design optimisation at the}

highest level of abstraction

09/14/17 4 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

On-line

testing

High-level

synthesis

High-level

synthesis for

on-line testability

 _{On-line testing resources will be On-line testing resources will be} inserted

inserted automatically automatically by the tool by the tool when the designer requires them

when the designer requires them

 _{Comparing alternative testing Comparing alternative testing}

techniques and choosing the most

techniques and choosing the most

appropriate in each particular case

appropriate in each particular case

will be facilitated.

09/14/17 5 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

On-line testing techniques

On-line testing techniques

 _{self-checking designself-checking design}

 _{on-line built-in self-test (BIST)on-line built-in self-test (BIST)}

 _{monitoring analogue characteristicsmonitoring analogue characteristics}

 _{In this work, we focus on In this work, we focus on self-} self-checking design.

09/14/17 6 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Self-checking design

Self-checking design

 _{CUT = Circuit Under CUT = Circuit Under} Test

Test

 _{The CUT is augmented The CUT is augmented} according to some

according to some error error detecting code

detecting code..

 _{Error detecting codes Error detecting codes} include :

include :

• parity codes_{parity codes}

• duplication codes_{duplication codes}

• several others_{several others}

Augmented CUT

Checker

Error

 _{Duplication codes Duplication codes form the basis of form the basis of} our technique.

09/14/17 7 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Duplication testing

Duplication testing

 _{CUT* is functionally equivalent to CUT.CUT* is functionally equivalent to CUT.}  _{Fault-secure by nature.Fault-secure by nature.}

CUT CUT*

Comparator

Error

09/14/17 8 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Physical vs. Algorithmic

Physical vs. Algorithmic

Duplication

Duplication

Physical duplication

Physical duplication

 _{OperaOperatorstors (hardware modules) are (hardware modules) are} physically duplicated

physically duplicated

 _{Results in more than 100% hardware Results in more than 100% hardware} overhead

overhead

Algorithmic duplication Algorithmic duplication

 _{OperaOperations tions (functions) are (functions) are} behaviouraly

behaviouraly duplicated duplicated

 _{Depending on circumstances, can Depending on circumstances, can} result in significant hardware savings

result in significant hardware savings

1 2 3

+1

+3

*1 +2

A1

M1

A2 A1

09/14/17 9 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Inversion Testing

Inversion Testing

 _{INV(CUT) is the functional “inverse” INV(CUT) is the functional “inverse”} of CUT.

of CUT.

Comparator

Error CUT

INV(CUT)

Functional Output Augmented CUT

09/14/17 10 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Physical vs. Algorithmic

Physical vs. Algorithmic

Inversion

Inversion

Physical Inversion

Physical Inversion

 _{Allied to physical duplication, has no Allied to physical duplication, has no} advantage over it, therefore it is of no

advantage over it, therefore it is of no

interest

interest

Algorithmic Inversion Algorithmic Inversion

 _{Allied to algorithmic duplicationAllied to algorithmic duplication}  _{Depending on circumstances, can Depending on circumstances, can}

result in more hardware savings than

result in more hardware savings than

the algorithmic duplication technique

the algorithmic duplication technique

1 2 3

+1

*2

-1 *1

A1

S1

M2 M1

09/14/17 11 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Conclusions

Conclusions

and future work

and future work

 _{Our first experiments (using the Our first experiments (using the}

MOODS

MOODS High-Level Synthesis Suite) High-Level Synthesis Suite)

have been encouraging.

have been encouraging.

 _{We are working towards automating We are working towards automating}

the on-line test resource insertion

the on-line test resource insertion

process, so that

process, so that no modification of no modification of

VHDL code will be required!!!

VHDL code will be required!!!

 _{Our system should be versatile Our system should be versatile}

enough to recognise and apply the

enough to recognise and apply the

most beneficial (duplication or

most beneficial (duplication or

inversion) technique for each module

inversion) technique for each module

in a given design.

in a given design.

 _{Future steps include fault simulation Future steps include fault simulation}

and investigating methods to test the

and investigating methods to test the

control path of our designs.

control path of our designs.

09/14/17 6 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Self-checking design

Self-checking design

 _{CUT = Circuit Under CUT = Circuit Under} Test

Test

 _{The CUT is augmented The CUT is augmented} according to some

according to some error error detecting code

detecting code..

 _{Error detecting codes Error detecting codes} include :

include :

• parity codes_{parity codes}

• duplication codes_{duplication codes}

• several others_{several others}

Augmented CUT

Checker

Error

 _{Duplication codes Duplication codes form the basis of form the basis of} our technique.

09/14/17 7 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Duplication testing

Duplication testing

 _{CUT* is functionally equivalent to CUT.CUT* is functionally equivalent to CUT.}  _{Fault-secure by nature.Fault-secure by nature.}

CUT CUT*

Comparator

Error

09/14/17 8 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Physical vs. Algorithmic

Physical vs. Algorithmic

Duplication

Duplication

Physical duplication Physical duplication

 _{OperaOperatorstors (hardware modules) are (hardware modules) are} physically duplicated

physically duplicated

 _{Results in more than 100% hardware Results in more than 100% hardware} overhead

overhead

Algorithmic duplication Algorithmic duplication

 _{OperaOperations tions (functions) are (functions) are}

behaviouraly

behaviouraly duplicated duplicated

 _{Depending on circumstances, can Depending on circumstances, can} result in significant hardware savings result in significant hardware savings

1 2 3

+1

+3

*1 +2

A1

M1

A2 A1

09/14/17 9 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Inversion Testing

Inversion Testing

 _{INV(CUT) is the functional “inverse” INV(CUT) is the functional “inverse”} of CUT.

of CUT.

Comparator

Error CUT

INV(CUT)

Functional Output Augmented CUT

09/14/17 10 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Physical vs. Algorithmic

Physical vs. Algorithmic

Inversion

Inversion

Physical Inversion Physical Inversion

 _{Allied to physical duplication, has no Allied to physical duplication, has no} advantage over it, therefore it is of no advantage over it, therefore it is of no interest

interest

Algorithmic Inversion Algorithmic Inversion

 _{Allied to algorithmic duplicationAllied to algorithmic duplication}  _{Depending on circumstances, can Depending on circumstances, can}

result in more hardware savings than result in more hardware savings than the algorithmic duplication technique the algorithmic duplication technique

1 2 3

+1

*2

-1 *1

A1

S1

M2 M1

09/14/17 11 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

Conclusions

Conclusions

and future work

and future work

 _{Our first experiments (using the Our first experiments (using the} MOODS

MOODS High-Level Synthesis Suite) High-Level Synthesis Suite)

have been encouraging. have been encouraging.

 _{We are working towards automating We are working towards automating}

the on-line test resource insertion the on-line test resource insertion process, so that

process, so that no modification of no modification of

VHDL code will be required!!!

VHDL code will be required!!!

 _{Our system should be versatile Our system should be versatile}

enough to recognise and apply the enough to recognise and apply the most beneficial (duplication or

most beneficial (duplication or

inversion) technique for each module inversion) technique for each module in a given design.

in a given design.

 _{Future steps include fault simulation Future steps include fault simulation}

and investigating methods to test the and investigating methods to test the control path of our designs.

control path of our designs.