262
CHAPT ER 7 MEMORY
As a simple example, consider using the 4 word
×
4-bit RAM chip shown in Fig- ure 7-5, as a building block to first make a 4-word
×
8-bit module, and then an 8-word
×
4-bit module. We would like to increase the width of the four-bit words and also increase the number of words. Consider first the problem of
increasing the word width from four bits to eight. We can accomplish this by simply using two chips, tying their CS chip select lines together so they are
both selected together, and juxtaposing their data lines, as shown in Figure 7-7.
Consider now the problem of increasing the number of words from four to eight. Figure 7-8 shows a configuration that accomplishes this. T he eight words are dis-
tributed over the two four-word RAMs. Address line A
2
is needed because there are now eight words to be addressed. A decoder for
A
2
enables either the upper or lower memory module by using the CS lines, and then the remaining address
lines A
and A
1
are decoded within the enabled module. A combination of these two approaches can be used to scale both the word size and number of
words to arbitrary sizes.
7.4 Commercial M emory M odules
Commercially available memory chips are commonly organized into standard configurations. Figure 7-9 Texas Instruments, 1991 shows an organization of
eight 2
20
-bit chips on a single-in-line memory module SIMM that form a 2
20
×
8 1MB module. T he electrical contacts numbered 1 – 30 all lie in a single line. For 2
20
memory locations we need 20 address lines, but only 10 address lines A0 – A9 are provided. T he 10-bit addresses for the row and column are
loaded separately, and the Column Address Strobe and Row Address Strobe sig- nals are applied after the corresponding portion of the address is made available.
Although this organization appears to double the time it takes to access any par-
A A
1
WR CS
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
4 ×
4 RAM
Q
7
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q 4
× 4 RAM
Figure 7-7 Two four-word by four-bit RAMs are used in creating a four-word by eight-bit RAM.
CHAPT ER 7 MEMORY
263
ticular memory location, on average, the access time is much better since only the row or column address needs to be updated.
T he eight data bits on lines DQ1 – DQ8 form a byte that is read or written in parallel. In order to form a 32-bit word, four SIMM modules are needed. As
with the other “active low” signals, the Write Enable line has a bar over the corre- sponding symbol
which means that a write takes place when a 0 is placed on this line. A read takes place otherwise. T he RAS line also causes a refresh
operation, which must be performed at least every 8 ms to restore the charges on the capacitors.
7.5 Read-Only M emory
When a computer program is loaded into the memory, it remains in the memory until it is overwritten or until the power is turned off. For some applications, the
program never changes, and so it is hardwired into a
read-only memory
A A
1
WR D
3
D
2
D
1
D
4 ×
4 RAM
Q
3
Q
2
Q
1
Q 4
× 4 RAM
1-to-2 decoder
1 A
2
CS CS
CS
Figure 7-8 Two four-word by four-bit RAMs are used in creating an eight-word by four-bit RAM.
W
264
CHAPT ER 7 MEMORY
ROM. ROMs are used to store programs in videogames, calculators, micro- wave ovens, and automobile fuel injection controllers, among many other appli-
cations.
T he ROM is a simple device. All that is needed is a decoder, some output lines, and a few logic gates. T here is no need for flip-flops or capacitors. Figure 7-10
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
Vcc CAS
DQ1 A0
A1 DQ2
A2 A3
Vss DQ3
A4 A5
DQ4 A6
A7 DQ5
A8 A9
NC DQ6
W Vss
DQ7 NC
DQ8 NC
RAS NC
NC Vcc
PIN NOMENCLATURE Address Inputs
Column-Address Strobe Data InData Out
No Connection Row-Address Strobe
5-V Supply Ground
Write Enable DQ1-DQ8
CAS A0-A9
NC RAS
Vcc Vss
W
Figure 7-9 Single-in-line memory module Texas Instruments, 1991.
Q
3
Q
2
Q
1
Q 00
01 10
11 A
A
1
2-to-4 decoder
Enable Location
Stored word
00 01
10 11
0101 1011
1110 0000
Figure 7-10 A ROM stores four four-bit words.
CHAPT ER 7 MEMORY
265
shows a four-word ROM that stores four four-bit words 0101, 1011, 1110, and 0000. Each address input 00, 01, 10, or 11 corresponds to a different stored
word.
For high-volume applications, ROMs are factory-programmed. As an alternative, for low-volume or prototyping applications, programmable ROMs PROMs are
often used, which allow their contents to be written by a user with a relatively inexpensive device called a
PROM burner
. Unfortunately for the early videog- ame industry, these PROM burners are also capable of reading the contents of a
PROM, which can then be duplicated onto another PROM, or worse still, the contents can be deciphered through reverse engineering and then modified and
written to a new, contraband game cartridge.
Although the PROM allows the designer to delay decisions about what informa- tion is stored, it can only be written once, or can be rewritten only if the existing
pattern is a subset of the new pattern. Erasable PROMs EPROMs can be writ- ten several times, after being erased with ultraviolet light for UVPROMs
through a window that is mounted on the integrated circuit package. Electrically erasable PROMs EEPROMs allow their contents to be rewritten electrically.
Newer
flash
memories can be electrically rewritten tens of thousands of times, and are used extensively in digital video cameras, and for control programs in
set-top cable television decoders, and other devices.
PROMs will be used later in the text for control units and for
arithmetic logic units
ALUs. As an example of this type of application, consider creating an ALU that performs the four functions: Add, Subtract, Multiply, and Divide on
eight-bit operands. We can generate a truth table that enumerates all 2
16
possible combinations of operands and all 2
2
combinations of functions, and send the truth table to a PROM burner which loads it into the PROM.
T his brute force
lookup table
LUT approach is not as impractical as it may seem, and is actually used in a number of situations. T he PROM does not have
to be very big: there are 2
8
×
2
8
combinations of the two input operands, and there are 2
2
functions, so we need a total of 2
8
×
2
8
×
2
2
= 2
18
words in the PROM, which is small by current standards. T he configuration for the PROM
ALU is shown in Figure 7-11. T he address lines are used for the operands and for the function select inputs, and the outputs are produced by simply recalling the
precomputed word stored at the addressed location. T his approach is typically faster than using a hardware implementation for the functions, but it is not
extensible to large word widths without applying some form of decomposition.
266
CHAPT ER 7 MEMORY
32-bit operands are standard on computers today, and a corresponding PROM ALU would require 2
32
×
2
32
×
2
2
= 2
66
words which is prohibitively large.
7.6 Cache M emory
