Simple Bus Architectures 8.2 Bridge-Based Bus Architectures
8.1 Simple Bus Architectures 8.2 Bridge-Based Bus Architectures
8.3 Communication Methodologies 8.4 Case Study: Communication on the Intel Pentium Architecture 8.5 Mass Storage 8.6 Input Devices8.7 Output Devices
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Simple Bus Architecture • A simplified motherboard of a personal computer top view: Motherboard IO Bus Board traces wires Connectors for plug-in cards Integrated Circuits Plug-in card IO bus connector Memory CPU Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Simplified Illustration of a Bus CPU Disk Memory Control C – C 9 Address A – A 31 Data D – D 31 Power GND, +5V, –15V Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 100 MHz Bus Clock Crystal Oscillator 1 0 1 0 1 0 1 0 Logical 0 0V Logical 1 +5V 10 ns Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring The Synchronous Bus • Timing diagram for a synchronous memory read adapted from [Tanenbaum, 1999]. Φ Address Data MREQ RD T 1 T 2 T 3 Leading edge Trailing edge Data valid Time Address valid Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring The Asynchronous Bus • Timing diagram for asynchronous memory read adapted from [Tanenbaum, 1999]. Address MSYN RD Data Time Memory address to be read MREQ SSYN Data valid Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Bus Arbitration • aSimple centralized bus arbitration; b centralized arbitration with priority levels; c decentralized bus arbitration. Adapted from [Tanenbaum, 1999]. Arbiter Bus grant Bus request 1 2 n . . . a Arbiter Bus grant level 0 Bus request level 0 1 2 n . . . b Bus grant Bus request 1 2 n . . . c Busy +5V Bus grant level k Bus request level k ... Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Bridge Based Bus Ar- chitecture • Bridging with dual Pentium II Xeon proces- sors on Slot 2. Source: http: www.intel.com. 800 MBsecParts
» Organisasi Komputer (T. Informatika)
» Overview 1.2 A Brief History
» Overview 3.2 Fixed Point Addition and Subtraction
» The Compilation Process 5.2 The Assembly Process
» Basics of the Microarchitecture 6.2 A Microarchitecture for the ARC
» The Memory Hierarchy 7.2 Random Access Memory
» Simple Bus Architectures 8.2 Bridge-Based Bus Architectures
» Interleave Factor MBsec 33 MBsec
» Modems 9.2 Transmission Media Communication
» Quantitative Analyses of Program Execution 10.2 From CISC to RISC
» PROBLEMS 1-1 PROBLEMS 2-1 The binary representation of the hexadecimal number 3B7F is choose one:
» PROBLEMS 4-1 Organisasi Komputer (T. Informatika)
» PROBLEMS 5-1 Organisasi Komputer (T. Informatika)
» Introduction Data Representation Arithmetic T he Instruction Set Architecture
» Languages and the Machine Datapath and Control Memory Input and Output Communication
» The Von Neumann M odel The System Bus M odel
» A Typical Computer System Organization of the Book
» Case Study: W hat Happened to Supercomputers?
» Introduction Trends in Computer Architecture
» Fixed Point Numbers Trends in Computer Architecture
» Floating Point Numbers Trends in Computer Architecture
» Case Study: Patriot M issile Defense Failure Caused by Loss of Precision
» Character Codes Trends in Computer Architecture
» Overview Fixed Point Addition and Subtraction
» Fixed Point M ultiplication and Division
» Floating Point Arithmetic Trends in Computer Architecture
» High Performance Arithmetic Trends in Computer Architecture
» Case Study: Calculator Arithmetic Using Binary Coded Decimal
» Hardw are Components of the Instruction Set Architecture
» Pseudo-Ops Trends in Computer Architecture
» Examples of Assembly Language Programs
» Accessing Data in M emory— Addressing M odes
» Subroutine Linkage and Stacks
» Input and Output in Assembly Language
» The Compilation Process Trends in Computer Architecture
» The Assembly Process Trends in Computer Architecture
» Linking and Loading Trends in Computer Architecture
» M acros Trends in Computer Architecture
» Case Study: Extensions to the Instruction Set – The Intel M M X
» Basics of the M icroarchitecture A M icroarchitecture for the ARC
» Hardw ired Control Trends in Computer Architecture
» Case Study: The VHDL Hardw are Description Language
» The M emory Hierarchy Random Access M emory
» Chip Organization Trends in Computer Architecture
» Commercial M emory M odules Read-Only M emory
» Virtual M emory Trends in Computer Architecture
» Advanced Topics Trends in Computer Architecture
» Case Study: The Intel Pentium M emory System
» Simple Bus Architectures Trends in Computer Architecture
» Bridge-Based Bus Architectures Trends in Computer Architecture
» MBsec 33 MBsec Communication M ethodologies
» Case Study: Communication on the Intel Pentium Architecture
» M ass Storage Trends in Computer Architecture
» Input Devices Trends in Computer Architecture
» Output Devices Trends in Computer Architecture
» M odems Trends in Computer Architecture
» Transmission M edia Trends in Computer Architecture
» Netw ork Architecture: Local Area Netw orks
» Communication Errors and Error Correcting Codes
» Netw ork Architecture: The Internet
» Case Study: Asynchronous Transfer M ode
» Quantitative Analyses of Program Execution
» Pipelining the Datapath Trends in Computer Architecture
» Overlapping Register W indow s
» VLIW M achines Case Study: The Intel IA-64 M erced Architecture
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