CHAPT ER 3 ARIT HMET IC
73
order to add +5.5
10
and
−
1.0
10
and obtain the correct result in one’s comple- ment, we add the end-around carry into the one’s position as shown. T his adds
complexity to our number circle, because in the gap between +0 and
−
0, there are valid numbers that represent fractions that are less than 0, yet they appear on
the number circle before
−
0 appears. If the number circle is reordered to avoid this anomaly, then addition must be handled in a more complex manner.
T he need to look for two different representations for zero, and the potential need to perform another addition for the end-around carry are two important
reasons for preferring the two’s complement arithmetic to one’s complement arithmetic.
3.3 Fixed Point M ultiplication and Division
Multiplication and division of fixed point numbers can be accomplished with addition, subtraction, and shift operations. T he sections that follow describe
methods for performing multiplication and division of fixed point numbers in both unsigned and signed forms using these basic operations. We will first cover
unsigned multiplication and division, and then we will cover signed multiplica- tion and division.
3.3.1
UNSIGNED MULTIPLICATION Multiplication of unsigned binary integers is handled similar to the way it is car-
ried out by hand for decimal numbers. Figure 3-10 illustrates the multiplication process for two unsigned binary integers. Each bit of the multiplier determines
whether or not the multiplicand, shifted left according to the position of the multiplier bit, is added into the product. When two unsigned n-bit numbers are
multiplied, the result can be as large as 2n bits. For the example shown in Figure 3-10, the multiplication of two four-bit operands results in an eight-bit product.
When two signed n-bit numbers are multiplied, the result can be as large as only
1 1
1 1
1 1
1 1
. .
. +5.5
10
–1.0
10
+ +4.5
10
1 1
+
1 1
. .
1
Figure 3-9 The end-around carry complicates addition for non-integers.
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CHAPT ER 3 ARIT HMET IC
2n-1+1 = 2n-1 bits, because this is equivalent to multiplying two n-1-bit unsigned numbers and then introducing the sign bit.
A hardware implementation of integer multiplication can take a similar form to the manual method. Figure 3-11 shows a layout of a multiplication unit for
four-bit numbers, in which there is a four-bit adder, a control unit, three four-bit registers, and a one-bit carry register. In order to multiply two numbers, the mul-
tiplicand is placed in the M register, the multiplier is placed in the Q register, and the A and C registers are cleared to zero. During multiplication, the rightmost bit
of the multiplier determines whether the multiplicand is added into the product at each step. After the multiplicand is added into the product, the multiplier and
the A register are simultaneously shifted to the right. T his has the effect of shift- ing the multiplicand to the left as for the manual process and exposing the next
bit of the multiplier in position q
. Figure 3-12 illustrates the multiplication process. Initially, C and A are cleared,
1 1 0 1 1 0 1 1
× 1 1 0 1
1 1 0 1 0 0 0 0
1 1 0 1 1 0 0 0 1 1 1 1
11
10
13
10
Multiplicand M Multiplier Q
143
10
Product P Partial products
Figure 3-10 Multiplication of two unsigned binary integers.
Multiplicand M m
m
1
m
2
m
3
a a
1
a
2
a
3
q q
1
q
2
q
3
Multiplier Q C
4–Bit Adder Shift and
Add Control Logic
Add 4
4
4 Shift Right
q A
Register
Figure 3-11 A serial multiplier.
CHAPT ER 3 ARIT HMET IC
75
and M and Q hold the multiplicand and multiplier, respectively. T he rightmost bit of Q is 1, and so the multiplier M is added into the product in the A register.
T he A and Q registers together make up the eight-bit product, but the A register is where the multiplicand is added. After M is added to A, the A and Q registers
are shifted to the right. Since the A and Q registers are linked as a pair to form the eight-bit product, the rightmost bit of A is shifted into the leftmost bit of Q.
T he rightmost bit of Q is then dropped, C is shifted into the leftmost bit of A, and a 0 is shifted into C.
T he process continues for as many steps as there are bits in the multiplier. On the second iteration, the rightmost bit of Q is again 1, and so the multiplicand is
added to A and the CAQ combination is shifted to the right. On the third iter- ation, the rightmost bit of Q is 0 so M is not added to A, but the CAQ combi-
nation is still shifted to the right. Finally, on the fourth iteration, the rightmost bit of Q is again 1, and so M is added to A and the CAQ combination is
shifted to the right. T he product is now contained in the A and Q registers, in which A holds the high-order bits and Q holds the low-order bits.
3.3.2
UNSIGNED DIVISION In longhand binary division, we must successively attempt to subtract the divisor
from the dividend, using the fewest number of bits in the dividend as we can. Figure 3-13 illustrates this point by showing that 11
2
does not “fit” in 0 or 01,
C
1
1 A
0 0 0 1 1 0 1
0 1 1 0 0 0 1 1
1 0 0 1 0 1 0 0
0 0 0 1 1 0 0 0
1 Q
0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1
Multiplicand M: 1 1 0 1
Initial values Add M to A
Shift Add M to A
Shift Shift no add
Add M to A Shift
Product
Figure 3-12 An example of multiplication using the serial multiplier.
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CHAPT ER 3 ARIT HMET IC
but does fit in 011 as indicated by the pattern 001 that starts the quotient. Computer-based division of binary integers can be handled similar to the way
that binary integer multiplication is carried out, but with the complication that the only way to tell if the dividend does not “fit” is to actually do the subtraction
and test if the remainder is negative. If the remainder is negative then the sub- traction must be “backed out” by adding the divisor back in, as described below.
In the division algorithm, instead of shifting the product to the right as we did for multiplication, we now shift the quotient to the left, and we subtract instead
of adding. When two n-bit unsigned numbers are being divided, the result is no larger than n bits.
Figure 3-14 shows a layout of a division unit for four-bit numbers in which there
is a five-bit adder, a control unit, a four-bit register for the dividend Q, and two five-bit registers for the divisor M and the remainder A. Five-bit registers are used
for A and M, instead of 4-bit registers as we might expect, because an extra bit is
1 1 0 0 1 0
0 1 1 1 1 1
R 1 1
Figure 3-13 Example of base 2 division.
Divisor M m
m
1
m
2
m
3
a a
1
a
2
a
3
q q
1
q
2
q
3
Dividend Q 5–Bit Adder
Shift and Add Sub
Control Logic Add
Sub 5
5
5 Shift Left
q A
Register a
4
a
4
Figure 3-14 A serial divider.
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77
needed to indicate the sign of the intermediate result. Although this division method is for unsigned numbers, subtraction is used in the process and negative
partial results sometimes arise, which extends the range from
−
16 through +15, thus there is a need for 5 bits to store intermediate results.
In order to divide two four-bit numbers, the dividend is placed in the Q register, the divisor is placed in the M register, and the A register and the high order bit of
M are cleared to zero. T he leftmost bit of the A register determines whether the divisor is added back into the dividend at each step. T his is necessary in order to
restore the dividend when the result of subtracting the divisor is negative, as described above. T his is referred to as
restoring division
, because the dividend is restored to its former value when the remainder is negative. When the result is
not negative, then the least significant bit of Q is set to 1, which indicates that the divisor “fits” in the dividend at that point.
Figure 3-15 illustrates the division process. Initially, A and the high order bit of M are cleared, and Q and the low order bits of M are loaded with the dividend
and divisor, respectively. T he A and Q registers are shifted to the left as a pair and the divisor M is subtracted from A. Since the result is negative, the divisor is
added back to restore the dividend, and q
is cleared to 0. T he process repeats by shifting A and Q to the left, and by subtracting M from A. Again, the result is
negative, so the dividend is restored and q is cleared to 0. On the third iteration,
A and Q are shifted to the left and M is again subtracted from A, but now the result of the subtraction is not negative, so q
is set to 1. T he process continues for one final iteration, in which A and Q are shifted to the left and M is sub-
tracted from A, which produces a negative result. T he dividend is restored and q is cleared to 0. T he quotient is now contained in the Q register and the remain-
der is contained in the A register.
3.3.3
SIGNED MULTIPLICATION AND DIVISION If we apply the multiplication and division methods described in the previous
sections to signed integers, then we will run into some trouble. Consider multi- plying
−
1 by
+
1 using four-bit words, as shown in the left side of Figure 3-16. T he eight-bit equivalent of +15 is produced instead of
−
1. What went wrong is that the sign bit did not get extended to the left of the result. T his is not a prob-
lem for a positive result because the high order bits default to 0, producing the correct sign bit 0.
A solution is shown in the right side of Figure 3-16, in which each partial prod-
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CHAPT ER 3 ARIT HMET IC
uct is extended to the width of the result, and only the rightmost eight bits of the result are retained. If both operands are negative, then the signs are extended for
both operands, again retaining only the rightmost eight bits of the result.
Signed division is more difficult. We will not explore the methods here, but as a
1 A
0 0 0 0 0 0 0
1 1 0 1
0 0 1 1 0 0 0 0
Q 1 1 1
1 1 1 0 1 1 1 0
1 0 0 0 1 0 0 0
Divisor M: 0 0 1 1
Initial values Shift left
Subtract M from A
Shift left Subtract M from A
0 0 0 0 0 1 1 1 0
Restore A Add M to A
1 0 0 0 1
1 1 1 0 1 1 0 0
1 1 0 0 Shift left
Subtract M from A 0 0 0 0 1
1 1 0 0 Restore A
0 0 0 0 0 1 1 1 0
Clear q
0 0 0 0 1 1 1 0 0
Clear q
0 0 0 0 0 1 0 0 1
Set q 1
0 0 0 1 1 1 1 0
0 0 1 0 0 0 1 0
Shift left Subtract M from A
0 0 0 0 1 0 0 1 0
Restore A 0 0 0 0 1
0 0 1 0 Clear q
Remainder Quotient
Figure 3-15 An example of division using the serial divider.
1 1 1 1 0 0 0 1
× 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1
+1
10
–1
10
+15
10
Incorrect; result should be –1 1 1 1 1
0 0 0 1 ×
1 1 1 1 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 +1
10
–1
10
–1
10
1 1 1 1 1 1 1 1
0 0 0 0 0
Figure 3-16 Multiplication of signed integers.
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79
general technique, we can convert the operands into their positive forms, per- form the division, and then convert the result into its true signed form as a final
step.
3.4 Floating Point Arithmetic
