Research Interests
•
VLSI Design and Test Test Compression and BIST, Fault Tolerance, Iterative Heuristics.
Recent Projects
•
Lead the VLSI test experiments at Stanford between 01 and 05.
•
Test data compression using compatibility classes.
Industrial Experience
•
Lead a major test cost saving operation with millions of annual savings.
Patents
•
Four US patents filed all related to VLSI test.
Recent Publications
•
Al-Yamani, A., E. Chmelar and M. Grinchuk, Segmented Addressable Scan Architecture, 23
rd
IEEE VLSI Test Symposium VTS05, Palm Springs, CA, May 1-
5, 2005. PATENT PENDING TECHNOLOGY
•
Al-Yamani, A., and E.J. McCluskey, BIST-Guided ATPG, 6
th
IEEE International Symposium on Quality Electronics Design ISQED05, San Jose, CA, March, 05.
•
Al-Yamani, A., and E. McCluskey, Test Quality for High Level Structural Test, ACM Transactions on Design Test of Electronic Systems TODAES05, Oct. 05.
•
McCluskey, E.J., Al-Yamani, Li, Tseng, Volkerink, Ferhani, Li, and Mitra,ELF- Murphy Data on Defects and Test Sets, 22
nd
IEEE VLSI Test Symposium VTS’04,
Napa Valley, CA, Apr. 25-28, 2004. STANFORD TEST EXPERIMENT.
Research Interests
•
VLSI Design and Test Test Compression and BIST, Fault Tolerance, Iterative Heuristics.
Recent Projects
•
Lead the VLSI test experiments at Stanford between 01 and 05.
•
Test data compression using compatibility classes.
Industrial Experience
•
Lead a major test cost saving operation with millions of annual savings.
Patents
•
Four US patents filed all related to VLSI test.
Recent Publications
•
Al-Yamani, A., E. Chmelar and M. Grinchuk, Segmented Addressable Scan
Architecture , 23
rd
IEEE VLSI Test Symposium VTS05, Palm Springs, CA, May 1- 5, 2005.
PATENT PENDING TECHNOLOGY
•
Al-Yamani, A., and E.J. McCluskey, BIST-Guided ATPG
, 6
th
IEEE International Symposium on Quality Electronics Design ISQED05, San Jose, CA, March, 05.
•
Al-Yamani, A., and E. McCluskey, Test Quality for High Level Structural Test
, ACM Transactions on Design Test of Electronic Systems TODAES05, Oct. 05.
•
McCluskey, E.J., Al-Yamani, Li, Tseng, Volkerink, Ferhani, Li, and Mitra, ELF-
Murphy Data on Defects and Test Sets , 22
nd
IEEE VLSI Test Symposium VTS’04, Napa Valley, CA, Apr. 25-28, 2004.
STANFORD TEST EXPERIMENT .
Research Interests
•
Modeling, simulating, and synthesizing VLSI hardware for cryptography and computer arithmetic operations.
Recent Projects
•
Design of efficient integrated circuits for the inverse computation in different finite fields.
•
Design of Elliptic Curve Cryptography Architectures using parallel multipliers.
Recent Publications
•
Adnan Abdul-Aziz Gutub and Alexandre F. Tenca, “Efficient Scalable VLSI Architecture for Montgomery Inversion in GFp”, Integration, the VLSI
Journal, Vol. 37, No. 2, pages 103-120, May 2004.
•
Adnan Abdul-Aziz Gutub, “VLSI CORE ARCHITECTURE FOR GFP ELLIPTIC CURVE CRYPTO PROCESSOR”, IEEE 10th International
Conference on Electronics, Circuits and Systems ICECS 2003, pages 84- 87, University of Sharjah, United Arab Emirates, December 14-17, 2003.
•
Adnan Abdul-Aziz Gutub and Alexandre F. Tenca, “ Efficient Scalable Hardware Architecture for Montgomery Inverse Computation in GFP”,
IEEE Workshop on Signal Processing Systems SIPS’03, pages 93-98, Seoul, Korea, August 27-29, 2003.
Research Interests
•
Modeling, simulating, and synthesizing VLSI hardware for cryptography and computer arithmetic operations.
Recent Projects
•
Design of efficient integrated circuits for the inverse computation in different finite fields.
•
Design of Elliptic Curve Cryptography Architectures using parallel multipliers.
Recent Publications
•
Adnan Abdul-Aziz Gutub and Alexandre F. Tenca, “ Efficient Scalable VLSI
Architecture for Montgomery Inversion in GFp”, Integration, the VLSI
Journal, Vol. 37, No. 2, pages 103-120, May 2004.
•
Adnan Abdul-Aziz Gutub, “ VLSI CORE ARCHITECTURE FOR GFP
ELLIPTIC CURVE CRYPTO PROCESSOR ”, IEEE 10th International
Conference on Electronics, Circuits and Systems ICECS 2003, pages 84- 87, University of Sharjah, United Arab Emirates, December 14-17, 2003.
•
Adnan Abdul-Aziz Gutub and Alexandre F. Tenca, “ Efficient Scalable
Hardware Architecture for Montgomery Inverse Computation in GFP”, IEEE Workshop on Signal Processing Systems SIPS’03, pages 93-98,
Seoul, Korea, August 27-29, 2003.
Professor Professor
Professor Professor
Research Interests
•
ASICSoC Design and Verification Methodologies, Digital System Design, Interconnection Networks, Switch Architectures, Telecommunication
protocols, Computer Cryptography and Asynchronous Design.
Recent Projects
•
Study of modified Multistage Interconnection Networks for Networks-on- Chips.
•
Design and Performance Evaluation of a Distributed Crossbar Scheduler.
Industrial Experience
•
6 years experience in ASIC DesignVerification, mostly as Chip Architect for AMCC and Zarlink Semiconductor. Worked on Network Processors,
SONET, Digital Wrapper, Reed Solomon Codecs, VDSL PHY Chipset, ATM framers, TDM and Ethernet Switches.
•
Directed product and field testing at Lambda Opticalsystems Corp building an all-optical MEMS-based carrier-class switch.
Patents
•
Patent Applications for VDSL aggregation line-rate circuitry.
Publications
•
Experimental Study of a Generic Router Architecture under MILE, IASTED97
•
Adaptive Message Routing for Compact Reconfigurable Router, IEEE ICECS97.
Research Interests
•
ASICSoC Design and Verification Methodologies, Digital System Design, Interconnection Networks, Switch Architectures, Telecommunication
protocols, Computer Cryptography and Asynchronous Design.
Recent Projects
•
Study of modified Multistage Interconnection Networks for Networks-on- Chips
.
•
Design and Performance Evaluation of a Distributed Crossbar Scheduler .
Industrial Experience
•
6 years experience in ASIC DesignVerification, mostly as Chip Architect for AMCC and Zarlink Semiconductor. Worked on Network Processors,
SONET, Digital Wrapper, Reed Solomon Codecs, VDSL PHY Chipset, ATM framers, TDM and Ethernet Switches.
•
Directed product and field testing at Lambda Opticalsystems Corp building an all-optical MEMS-based carrier-class switch.
Patents
•
Patent Applications for VDSL aggregation line-rate circuitry.
Publications
•
Experimental Study of a Generic Router Architecture under MILE ,
IASTED97
•
Adaptive Message Routing for Compact Reconfigurable Router , IEEE
ICECS97.
Research Interests
•
Design Automation and FPGA based Synthesis, Reconfigurable Computing, Hardware Software Co-Design and Embedded
Systems, Computer Architecture, Parallel and distributed processing
Recent Projects
•
Software Pipelining for Reconfigurable Instruction Set Processors
•
Design and Implementation of a Reconfigurable Network Interface
•
Load Balancing for Parallel Visualization of Blood Head Vessel Angiography on Cluster of PCs
Recent Publications
•
A. .R. Naseer, et al., “Adaptive Pre-Task Assignment scheduling strategy for heterogeneous distributed raytracing system”, Journal IEICE EE , vol. 1,
No. 13, October 2004, pp 373-379
•
A. R. Naseer, et al., “Direct Mapping of RTL Structures onto LUT-Based FPGAs”, IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems, Volume 17, July 1998, pp. 624-631
•
A. R. Naseer, FAST : FPGA Targeted RTL Structure Synthesis Technique, Proc. of IEEEACM 7th International Conference on VLSI Design94 January
1994, pp. 21-24 bagged the BEST PAPER AWARD
Research Interests
•
Design Automation and FPGA based Synthesis, Reconfigurable Computing, Hardware Software Co-Design and Embedded
Systems, Computer Architecture, Parallel and distributed processing
Recent Projects
•
Software Pipelining for Reconfigurable Instruction Set Processors
•
Design and Implementation of a Reconfigurable Network Interface
•
Load Balancing for Parallel Visualization of Blood Head Vessel Angiography on Cluster of PCs
Recent Publications
•
A. .R. Naseer, et al., “Adaptive Pre-Task Assignment scheduling strategy for
heterogeneous distributed raytracing system”, Journal IEICE EE , vol. 1, No. 13, October 2004, pp 373-379
•
A. R. Naseer, et al., “Direct Mapping of RTL Structures onto LUT-Based
FPGAs”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume 17, July 1998, pp. 624-631
•
A. R. Naseer, FAST : FPGA Targeted RTL Structure Synthesis Technique,
Proc. of IEEEACM 7th International Conference on VLSI Design94 January 1994, pp. 21-24
bagged the BEST PAPER AWARD
Research Interests
•
Processor Micro-architecture, Multiprocessors and Interconnection Networks, Parallel programming environments and compilation
techniques
Recent Projects
•
Beyond Instruction-Level Parallelism in Processor Architecture, AUC, 2002-2003.
•
Shared Channels in Interconnection Networks, AUC 1999-2000.
Recent Publications
•
Mudawar M., Scalable Cache Memory Design for Large-Scale SMT Architectures, Proc. of the 3rd Workshop on Memory Performance
Issues, June 20-23 2004, Munich, Germany .
•
Mudawwar M. and Saad A., The k-ary n-cube Network and its Dual: a Comparative Study, in Proceedings of the 13th IASTED
International Conference on Parallel and Distributed Computing and Systems, August 21-24, 2001, Anaheim, California, pages 254-259.
•
Mudawwar M. and Mameesh R., Region Broadcasting in k-ary m- way Networks, in Proc. of the ISCA 13th International Conference
on Parallel and Distributed Computing Systems, August 8-10, 2000, Las Vegas, Nevada, pages 268-274.
Research Interests
•
Processor Micro-architecture, Multiprocessors and Interconnection Networks, Parallel programming environments and compilation
techniques
Recent Projects
•
Beyond Instruction-Level Parallelism in Processor Architecture ,
AUC, 2002-2003.
•
Shared Channels in Interconnection Networks, AUC 1999-2000.
Recent Publications
•
Mudawar M., Scalable Cache Memory Design for Large-Scale SMT
Architectures , Proc. of the 3rd Workshop on Memory Performance
Issues, June 20-23 2004, Munich, Germany .
•
Mudawwar M. and Saad A., The k-ary n-cube Network and its Dual:
a Comparative Study , in Proceedings of the 13th IASTED
International Conference on Parallel and Distributed Computing and Systems, August 21-24, 2001, Anaheim, California, pages 254-259.
•
Mudawwar M. and Mameesh R., Region Broadcasting in k-ary m-
way Networks , in Proc. of the ISCA 13th International Conference
on Parallel and Distributed Computing Systems, August 8-10, 2000, Las Vegas, Nevada, pages 268-274.
Research Interests
•
3G4G wireless networking – Wi-Fi and Wi-Max networks, Performance analysis and capacity for wireless networks, Simulation and modeling
Recent Projects
•
Wireless Local Area Networks Integration for Mobile Networks Operators, 2005.
•
E-Tourism Promoter – An Internet Assisted Location Tracker and Map Reader for Tourists, 2005.
Industrial Experience
•
5 years with Nortel Networks, Ottawa, Canada
Patents
•
3 Patent applications in the area of radio resource managements
Recent Publications
•
“Performance of Inter-Base Station Soft Handoff for 3G CDMA Networks,” ICMSAO’05.
•
“Non-blocking FCFS algorithm for Data Services over Wireless CDMA Networks,” ICMSAO’05
•
“Buffer Occupancy Analysis For A Broadband Polling-Based WLAN,” Net- Con2003
Research Interests
•
3G4G wireless networking – Wi-Fi and Wi-Max networks, Performance analysis and capacity for wireless networks, Simulation and modeling
Recent Projects
•
Wireless Local Area Networks Integration for Mobile Networks Operators ,
2005.
•
E-Tourism Promoter – An Internet Assisted Location Tracker and Map Reader for Tourists
, 2005.
Industrial Experience
•
5 years with Nortel Networks, Ottawa, Canada
Patents
•
3 Patent applications in the area of radio resource managements
Recent Publications
•
“ Performance of Inter-Base Station Soft Handoff for 3G CDMA Networks
,” ICMSAO’05.
•
“ Non-blocking FCFS algorithm for Data Services over Wireless CDMA
Networks, ” ICMSAO’05
•
“ Buffer Occupancy Analysis For A Broadband Polling-Based WLAN
,” Net- Con2003
Research Interests
•
Network Design, Network Management, Iterative Heuristics, Constraint Satisfaction Problems CSP, and Case-Based Reasoning CBR.
Recent Projects
•
A Framework for Integration of Web-based Network Management and Management by Delegation, 2004-2006.
•
Web Engineering Modern Iterative Heuristics to Solve Hard Computer Network Design Problems, 2004-2005.
Industrial Experience
•
Senior Automation Testing Specialist, Siemens, Ottawa, Canada 1999-2002.
Recent Publications
•
M. H. Sqalli, and S. Sirajuddin, “Static Weighted Load-balancing for XML-
