INTRODUCTION Connection Oriented Network

52 ATM NETWORKS Correction Mode No error detected No action Single-bit error detected correction Multiple-bit error detected cell discard No error detected No action Error detected cell discard Detection Mode Figure 3.4 The header error control state machine. Bit 2 is set to 0 if no congestion has been experienced, and to 1 if congestion has been experienced. Also, for a user data cell, bit 1 is used by the ATM Adaptation Layer 5. It is set to 0 if the service data unit SDU type is zero, and to 1 if the SDU type is one. For OAM data cells, two types are defined. In addition, a resource management RM cell is defined, and is used in conjunction with the available bit rate ABR mechanism, which is a feedback-based congestion control mechanism see Chapter 7. The cell loss priority CLP bit is used to indicate whether a cell can be discarded when congestion arises inside the network. If a cell’s CLP bit is set to one, then the cell can be discarded. On the other hand, if the cell’s CLP bit is set to 0, then the cell cannot not be discarded. The use of the CLP bit is discussed in Chapter 4. The header error control HEC field is used to correct single-bit and to detect multiple- bit transmission errors in the header. CRC is used with a 9-bit pattern given by the polynomial x 8 + x 2 + x + 1. The HEC field contains the 8-bit FCS obtained by using the formula of: the first 32 bits of the header x 2 8 divided by the above pattern. The state machine that controls the head error correction scheme see Figure 3.4 is implemented in the physical layer see Section 3.4. At initialization, the receiver’s state machine is set to the correction mode. Each time that a cell arrives, the CRC is carried out. If no errors are found, then the cell is allowed to proceed to the ATM layer and the state machine remains in the correction mode. If a single-bit error is detected, then the error is corrected and the cell is allowed to proceed to the ATM layer, but the state machine switches to the detection mode. If a multi-bit error is detected, then the cell is discarded and the state machine switches to the detection mode. In detection mode, then the CRC is carried out each time that a cell comes in. If a single-bit or a multi-bit error is detected, then the cell is discarded and the state machine remains in the detection mode. If no errors are detected, then the cell is allowed to proceed to the ATM layer and the state machine shifts back to the correction mode.

3.3 THE ATM PROTOCOL STACK

The ATM protocol stack is shown in Figure 3.5. It consists of the physical layer, the ATM layer, the ATM Adaptation Layer, and higher layers that permit various applications to run on top of ATM. It is important to note that the ATM layer and the ATM adaptation layer do not correspond to any specific layers of the OSI reference model; it is erroneous to refer to the ATM layer as the data link layer.