The Physical Medium-Dependent PMD Sublayer

THE ATM SWITCH ARCHITECTURE 59 on each input interface and is not very large, which makes the table search time to be minimal. ATM switch architectures can be grouped into the following three classes: space- division, memory sharing , and medium sharing. Space-division switch architectures are based on multistage interconnection networks MIN. A MIN consists of a network of interconnected switching elements arranged in rows and columns. A shared memory switch architecture uses a single memory for storing all of the incoming cells from the input ports. Cells stored in the memory are organized into linked lists, one per output port. The cells in each linked list are transmitted out of the switch by its associated output port. Finally, in a medium sharing switch, all arriving cells at the switch are synchronously transmitted onto a bus. Each output port i sees all of the cells transmitted on the bus, and receives those cells whose destination is output port i. In front of each output port, there is a buffer, where the cells can wait until they are transmitted out. The shared memory switch is the dominant switch architecture and is described below.

3.6.1 The Shared Memory Switch

The main feature of this switch architecture is a shared memory that is used to store all of the cells coming in from the input ports. The cells in the shared memory are organized into linked lists – one per output port see Figure 3.9. The shared memory is dual ported; that is, it can read and write at the same time. At the beginning of each slot, each input port that holds a cell, writes it into the shared memory. At the same time, each output port reads the cell from the top of its linked list assuming that the linked list has a cell and transmits it out. If N is the number of inputoutput ports, then one slot can write up to N cells into the shared memory and transmit up to N cells out of the shared memory. If the speed of transmission on each incoming and outgoing link is V , then the switch can keep up at maximum arrival rate, if the memory’s bandwidth is at least 2NV. The total number of cells that can be stored in the memory is bounded by the memory’s capacity B, expressed in cells. Modern shared memory switches have a large shared memory and can hold hundreds of thousands of cells. The total number of cells allowed to queue for each output port i is limited to B i , where B i B . That is, the linked list associated with output port i cannot exceed B i . This constraint is necessary for avoiding starvation of other output ports when output port i gets hot ; that is, when a lot of the incoming traffic goes to that particular port. When this happens, the linked list associated . . . ... . . . ... Shared memory 1 N N 1 Figure 3.9 A shared memory switch.