V V Paolo IDF session 030305

36 Third party marks and brands are the property of their respective owners 1 10 100 1000 0.2 0.4 0.6 0.8 1.0 1.2 I ON mAum I OFF nAum PMOS NMOS 90 nm 2002 2004 65 nm 2004

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Improved Transi stor Performance Improved Transi stor Performance 65 nm transistors increase drive current 10 65 nm transistors increase drive current 10 - - 15 with 15 with enhanced strain enhanced strain 37 Third party marks and brands are the property of their respective owners 1 10 100 1000 0.2 0.4 0.6 0.8 1.0 1.2 I ON mAum I OFF nAum PMOS NMOS 90 nm 2002 2004 65 nm 2004

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Improved Transi stor Performance Improved Transi stor Performance 65 nm transistors can alternatively provide ~4x leakage 65 nm transistors can alternatively provide ~4x leakage reduction reduction No other company has matched these performance No other company has matched these performance - - leakage leakage capabilities capabilities Power Saving Feature 38 Third party marks and brands are the property of their respective owners Strai ned Si l i con Strai ned Si l i con y y Intel 90nm strain silicon has been in volume Intel 90nm strain silicon has been in volume production since 2003 production since 2003 y y Observed leakage reduction 1.2V Observed leakage reduction 1.2V – – N N - - Channel Channel - - 5X Reduction 5X Reduction – – P P - - Channel Channel - - 5X Reduction 5X Reduction y y Intel 65nm technology has been successfully Intel 65nm technology has been successfully demonstrated in 2004 using demonstrated in 2004 using “ “ 2 2 nd nd Generation Strained Generation Strained Silicon Silicon ” ” y y Observed a further leakage reduction 1.0V from Observed a further leakage reduction 1.0V from 90nm process 90nm process – – N N - - Channel Channel - - 4X Reduction 4X Reduction – – P P - - Channel Channel - - 4X Reduction 4X Reduction The power challenge 39 Third party marks and brands are the property of their respective owners Reduced Gate Capaci tance at 65nm Reduced Gate Capaci tance at 65nm Gate Substrate Source Drain C GATE Power Saving Feature • Gate oxide thickness is held constant at 1.2 nm to avoid increased gate leakage • Gate capacitance C GATE reduced ~20 due to smaller gate length 35 nm • Lower gate capacitance reduces chip active power • Combination of higher drive current and lower gate capacitance provides ~1.4x increase in switching frequency 40 Third party marks and brands are the property of their respective owners Gate Substrate Drain Source Oxide C WIRE C GATE Gate Substrate Source Drain C WIRE C JUNCT C GATE Lower Juncti on Capaci tance Lower Juncti on Capaci tance Speeds up Ci rcui ts Speeds up Ci rcui ts 1- CjC total 1 SOI reduces junction capacitance under 5 of total, but not gate or wire capacitance The power challenge 41 Third party marks and brands are the property of their respective owners Planar CMOS Bulk CMOS vs. PDSOI Gate SiO 2 SiO 2 Silicon Substrate Partially Depleted SOI Gate SiO 2 SiO 2 Silicon Substrate Buried Oxide Silicon Substrate For illustration only 42 Third party marks and brands are the property of their respective owners Intel Already Has the Lowest Junction Intel Already Has the Lowest Junction Capacitance 180nm data Capacitance 180nm data S. Tyagi, IEDM 2000 Intel achieves the industry’s lowest junction capacitance without SOI, thereby avoiding the cost of SOI The power challenge Intel 0.40 0.60 0.80 1.00 1.20 1.40 1.60 -0.5 0.5 1 1.5 Bias V N+PWell P+Nwell Wang, EDL Oct.00 Mehrotra IEDM 99 Imai, IEDM 99 Yoshimura, VLSI 00 Diaz, VLSI 00 Yeap, VLSI 00 Junction Capacitance fFµm 2 Intel 43 Third party marks and brands are the property of their respective owners • All 3 elements of SOI performance diminish with scaling - Gain for 90nm node: 3-10 depending on history guardband 0.18um 130nm 90nm F.O.=1 Inverter 16 13 11 F.O.=4 Inverter 8 7 6 3-Input NAND 20 17 14 Average 15 12 10 History Guardband -5 -6 -7 NET 10 6 3 Analysis ignores interconnect load, which reduces SOI gain further K. Mistry, VLSI 2000 Net Impact of SOI Goes Down wi th Net Impact of SOI Goes Down wi th Each Generati on Each Generati on The power challenge 44 Third party marks and brands are the property of their respective owners Intel Intel ’ ’ s bul k CMOS has extremel y l ow s bul k CMOS has extremel y l ow Cj Cj y y Low Low Cj Cj =~ 0.1 x C total =~ 0.1 x C total