nm transistor gate oxide nm transistor gate oxide
25
Third party marks and brands are the property of their respective owners
65nm Technol ogy Hi ghl i ghts 65nm Technol ogy Hi ghl i ghts
y y
Intel 65 nm generation logic technology provides Intel 65 nm generation logic technology provides
improved performance and reduced power: improved performance and reduced power:
– –
1.2 nm transistor gate oxide 1.2 nm transistor gate oxide
– –
35 nm transistor gate length 35 nm transistor gate length
– –
Enhanced strained silicon technology Enhanced strained silicon technology
– –
8 layers of copper interconnect 8 layers of copper interconnect
– –
Low Low
- -
k dielectric k dielectric
y y
This technology is being demonstrated on fully This technology is being demonstrated on fully
functional 70 functional 70
Mbit Mbit
SRAM chips with 0.5 billion SRAM chips with 0.5 billion
transistors transistors
y y
Intel Intel
’ ’
s 65 nm technology is on track for delivery in s 65 nm technology is on track for delivery in
2005 2005
26
Third party marks and brands are the property of their respective owners
Gate oxi de scal i ng has sl owed Gate oxi de scal i ng has sl owed
Source: Intel The power
challenge
I
DSat
1
µ
V
DD
–V
T 2
2 Lg
W
ε
o
ε
s
1
t
ox
~
Mobi lity
1 10
1990 1995
2000 2005
Gate Oxide Thickness
nm
1 10
1.2 nm
0.5 µm
0.35 µm
0.25 µm
0.18 µm
0.13 µm
90nm 65nm
Slower scaling of one parameter can be compensated by speeding up another
Tra nsi
sto r
per for
ma nce
27
Third party marks and brands are the property of their respective owners
65nm Process 65nm Process
- -
Transi stor Transi stor
Strained silicon enhanced for Strained silicon enhanced for
performance and power efficiency performance and power efficiency
35nm 35nm
Source: Intel
28
Third party marks and brands are the property of their respective owners
65 nm Generati on Interconnects 65 nm Generati on Interconnects
M8
M7
M6
M5 M4
M3 M2
M1
• Metal 8 layer is added for improved density and performance
1 more layer than 90 nm generation
• Low-k carbon doped oxide dielectric reduces interconnect
capacitance
improved from 90 nm generation
• Interconnect capacitance is reduced by use of low-k dielectric
and by ~0.7x line length scaling
• Lower capacitance improves interconnect performance and
reduces chip power
Power Saving
Feature
29
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130nm 130nm
90nm 65nm
200mm 300mm
300mm 300mm
2000 2001
2002 2003
2004 Defect
Density log scale
Two Years
Defect Reducti on Trend Defect Reducti on Trend
65 nm yield on same improvement rate with 2 years offset 65 nm yield on same improvement rate with 2 years offset
30
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Ful l y Functi onal Devi ces on Intel Ful l y Functi onal Devi ces on Intel
’ ’
s s
65nm Process 65nm Process
Fully functional 70 Mbit SRAM ~110 mm
~110 mm
2 2
die size die size
0.5 billion transistors 0.5 billion transistors