Direct Switching

26.4.1 Direct Switching

voltage pulses based on relatively low voltage semiconductors devices are analyzed. The study begins with the most common The most straightforward technique for high-voltage pulse configurations for pulse generation that switch the HV voltage generation consists in switching directly the voltage from a dc directly into the load, using stacks of series semiconductors.

capacitor bank charged with high voltage into the load, using The dc–dc isolated converter topologies, forward, flyback,

a floating or a grounded switch, as shown in Fig. 26.26 and full-bridge, and half-bridge, which can be modified to produce Fig. 26.28, respectively. high-voltage rectangular repetitive pulses, with techniques that enable the use of relatively low semiconductor devices, are

26.4.1.1 Floating Switch

presented in the next section. Here, the use of a step-up Consider the circuit in Fig. 26.26, where the HV power supply, transformer provides galvanic isolation and further increases PS, V dc charges an energy storage capacitor bank C dc . The PS the output voltage pulse amplitude, although the transformer internal resistance added by the switch and wiring ohmic resis- presents limitations to its use. In order to overcome various tances is represented by r dc that limits the maximum charging technical hitches in assembling a unique high-voltage cir- current. Sometimes, a series inductor L aux is also added, which cuit, stacked associations of lower voltage topologies are also acts as a current limiter and causes some boost of the capacitor discussed with and without the use of output transformers. voltage during the charging period. Finally, the mature Marx generator pulse power topology is dis-

The voltage is modulated into the load by the series float- cussed with the intensive use of semiconductors. This concept ing switch Sp, which operates with duty ratio D. The switch-on

26 Solid State Pulsed Power Electronics 685 L aux

FIGURE 26.26 Direct modulator simplified circuit with floating switch. FIGURE 26.28 Direct modulator simplified circuit with grounded switch.

v V dc

if the S off time, T −t on , is enough for the PS V dc to charge C dc . Following, during t on , the energy delivered to the load is

V dc 2

t on . (26.5)

R L C dc For PP applications, only a small fraction of the stored energy should be transferred to the output during the pulse mode,

FIGURE 26.27 Typical RC discharge waveform. otherwise the pulse voltage has a typical RC discharge wave- form, as shown in Fig. 26.27, and not an almost rectangular

and switch-off control applies the full bank voltage to the load shape, as shown in Fig. 26.25. with the pulse width and frequency being controlled by the gate

For a resistive load, the pulse voltage decay V dcf can be

trigger. Supposing C dc charged with V dc , when S m is on, during calculated as t on , the C dc capacitor applies a voltage V dc into the load. During

this period, the inductance L aux limits the discharge of the PS

V dcf =V dci e RLCdc . (26.6) to the load.

If the load has capacitive behavior, an auxiliary circuit must Considering a resistive load R L , the capacitance of the C dc

be added to discharge the load capacitance to zero after the capacitor (Fig. 26.26 circuit) can be determined according to voltage pulse. For low duty ratio operation or low-power oper- energy delivered to the load. For the required pulse voltage

ation, a permanent parallel resistor R a1 can be connected to the

load, which must hold-off the applied voltage. The R a1 value

depends on its average power dissipation

R a1 where V C dcf is the capacitor voltage at the end of pulse, t on , and V C dci is the capacitors voltage immediately before the pulse.

and the required load voltage fall time. Considering (26.7), the difference between (26.4) and (26.5) is As an alternative, for high duty ratio operation or high- the energy stored in the C dc capacitor at end of pulse mode,

power operation, it is preferable to use an auxiliary series switch E C dcf ,

S a with R a2 to short the load after the pulse. In this case, the value of R a2 can be significantly reduced.

E C dci −E 0 =E C dcf , (26.8) The main advantages of Fig. 26.26 topology are associated with the generation of voltage pulses with low rise time, low where (26.8) for this case results in voltage droop, and also the flexibility to change the frequency and duty ratio operation. However, the pulse characteristics are

C dc V 2 V dc 2 dc C dc 0 V dc ) 2

(26.9) limited by the energy stored in the capacitor bank and on the

t on =

2 performance and power dissipated in the switches, and also on

considering that V C dc . Equating (26.9), the capacitor the rate of charge of C dc .

dci =V

value should satisfy the condition The energy initially stored in the C dc capacitor is

C dc V dc 2

2t on

E C dci =

C dc ≥

R L (1

686 L. Redondo and J. F. Silva Considering (26.3) through (26.10), it is mandatory to store in

Finally, the PS V dc must recharge the 20 J, plus 4 J (i.e.,

C dc an energy greater than five times the pulse energy in order 20% losses) in T −t on = 625 µs, then to have an output voltage droop better than 10%, but if a 1% voltage droop is expected, a 50 times storage energy is required,

E 0 20 +4

= 38.4 kW. which may impose limits to the design of the modulator.

P V dc =

+P loss =

625 × 10 −6 In addition, the V dc power supply must be able to recharge the C dc capacitor with an energy equal to the delivered pulse

T −t on

26.4.1.2 Ground Switch

energy, E 0 , plus losses, during the charging, T −t on , and pulse, It is possible to connect the switch S m referenced to ground and t on , periods

the C dc capacitor floating as shown in Fig. 26.28. Considering Fig. 26.27 circuit, when S p is off, the C

E 0 dc capacitor is charged P V dc =

+P loss .

(26.11) through the load. Supposing C dc charged with V dc , when S m

T −t on

turns on the positive terminal of C dc is grounded and a voltage

of V

dc is applied into the load. The main advantage of Fig. 26.28 configuration in relation

During the initial charging of the capacitor C dc , the PS takes a

longer time in order to limit the power dissipation in the R dc to Fig. 26.26 is that S m is grounded, which makes the trigger- resistor. ing process easier. However, in the Fig. 26.28 circuit, during the The main disadvantages associated with the circuit in pulse period t on , the V dc power supply is shorted, increasing Fig. 26.6 are the S m switch floating trigger terminals, resulting dramatically the power dissipation in R dc , which is a significant in a trigger signal that must be transmitted with galvanic isola- disadvantage that limits the operation to very low duty ratios.

tion. Also, switch S m must hold the total V dc voltage during the

off period, T −t If inductive-type loads are to be connected in both circuits, on , and conduct the load current during the on period.

it is mandatory to use a free wheeling diode in parallel with the load to reset it after the pulse and, also, to maintain the

E XAMPLE 26.5 Consider the HV pulse modulator of

magnetic energy continuity.

Fig. 26.26, where V dc = 20 kV. Calculate the value of the capacitor C dc for applying 50 µs, 1600 Hz, into a

26.4.1.3 Series Stacks of Semiconductors

R L supply, V dc , considering 20% losses during the charging

Considering the dozens of kilovolt range pulse amplitude in the and pulse modes.

majority of pulsed power applications and the limited maxi- mum reverse voltage of semiconductor switches, such as power

BJT, MOSFET, IGBT, GTO, and IGCT, it is necessary to con- with V dc and a voltage droop of 5%, then (26.7)

S OLUTION . Considering the capacitor C dc initially charged

nect many semiconductors in series to assemble the S m and S a switches in Fig. 26.26 and Fig. 26.28, as shown in Fig. 26.29

As seen, sharing resistors for steady state and RCD snubber circuits for transient voltage balance are needed for on–off - which results (26.3)

V C dci

controlled semiconductors. In addition, it is complex to syn- chronously trigger many devices in series, placed at different

2t on

floating high-voltage potentials.

Gate-control delay techniques, or generalized cascades, are used to force the synchronized operation of semiconductors

with mismatched switching on/off characteristics [42]. is

Choosing a 1.2 µF, then the energy stored in C dc initially

Nevertheless, in order to prevent shutdown of a series- stacked semiconductor switch due to a defect arising in one

E dc × 10 −6

C dc V 2 1.2 semiconductor, redundant switches are, usually, included in the

C dci =

2 = 240 J.

series, about 20% more, such that the surviving semiconduc- tors share the voltage and the failed semiconductor is still able

The energy delivered to the pulse is to carry the load current. This is true since the power switches used are built to short circuit when failing [43].

In order to decrease the voltage hold-off stress on the semi-

= 20 J.

conductors, it is possible to add a high-voltage step-up pulse transformer in the output, further increasing the output volt-

This means that after the pulse, the energy stored in age to the desired amplitude. However, several following issues the C dc capacitor is 220 J, corresponding to a final pulse

must be taken into consideration before designing the circuit voltage of 19.149 V that is 4.2% voltage droop.

26 Solid State Pulsed Power Electronics 687

Galvanic isolation & gate circuits L aux

FIGURE 26.29 Series-stacked semiconductor topology for high-voltage pulse generation.

1. The parasitic elements (i.e., distributed capacitance on the semiconductors. In this section, the focus is placed and leakage inductance) normally associated with the on the particular characteristics that enable high-voltage pulse assembling of the transformer impose limitations to the generation, using relatively low-voltage semiconductor devices. output pulse waveform, degrading the pulse rise time

As the objective is to generate high-voltage pulses at the and voltage plateau;

output, several changes must be introduced in the typical

2. The transformer core volt-seconds product limits the topologies and operating conditions of these circuits. The most transformer flexibility to accommodate different oper- obvious is the elimination of the output LC filter used to keep ating conditions, such as, duty ratio and frequency;

the output voltage nearly constant.

3. After the pulse, it is mandatory to reset the transformer In the following analysis, it is considered that the semi- core magnetic flux back to the initial status before the conductors switches have ideal switching behavior, instanta- next pulse, which imposes an auxiliary circuit.

neous commutation times, zero voltage drop, and zero leakage current.

Some of the topologies used in power electronics, designed for dc–dc isolated converters, can be specially modified for pulse generation, where the addition of the transformer gives

26.4.2.1 Forward Topology

the galvanic insulation and contributes to the reduction of The simplified forward-type circuit used to generate negative the hold-off voltage in the semiconductors as described in the unipolar high-voltage pulses into a load is shown in Fig. 26.30 following sections.

and the theoretical key waveforms are shown in Fig. 26.31. For positive unipolar pulses, the ground should be placed on the