MOSFET Switching Characteristics

4.4.3 MOSFET Switching Characteristics

Since the MOSFET is a majority carrier transport device, it is inherently capable of a high frequency operation [5–8]. But still the MOSFET has two limitations:

1. High input gate capacitances.

2. Transient/delay due to carrier transport through the FIGURE 4.14 Small-signal equivalent circuit including MOSFET out- drift region. put resistance.

As stated earlier the input capacitance consists of two com- ponents: the gate-to-source and gate-to-drain capacitances. junction capacitances by applying Miller theorem to Fig. 4.15a. The input capacitances can be expressed in terms of the device Using Miller theorem, the total input capacitance, C in , seen

between the gate-to-source is given by,

iD

C in =C gs + (1 + g m R L )C gd (4.12)

Slope = gm

The frequency response of the MOSFET circuit is limited by

ID

the charging and discharging times of C in . Miller effect is inherent in any feedback transistor circuit with resistive load that exhibits a feedback capacitance from the input and output. The objective is to reduce the feedback gate-to-drain resistance. The output capacitance between the drain-to-source, C ds , does

not affect the turn-on and turn-off MOSFET switching char- acteristics. Figure 4.16 shows how C gd and C gs vary under

FIGURE 4.13 Linearized i D vs v GS curve with operating dc point (Q).

increased drain-source, v Ds , voltage.

56 I. Batarseh

(a)

(b)

FIGURE 4.15 (a) Small-signal model including parasitic capacitances and (b) equivalent circuit using Miller theorem.

Capacitance The fly back diode D is used to pick up the load current when

C gs

the switch is off. To simplify the analysis we will assume the load inductance is L 0 large enough so that the current through

it is constant as shown in Fig. 4.17b.

A. Turn-on Analysis Let us assume initially the device is off,

C the load current, I 0 gd , flows through D as shown in the Fig. 4.18a v GG = 0. The voltage v DS =V DD and i G =i D . At t =t 0 , the

voltage v GG is applied as shown in Fig. 4.19a. The voltage across C GS starts charging through R G . The gate–source volt-

age, v GS , controls the flow of the drain-to-source current i D . Let us assume that for t 0 ≤t<t 1 ,v GS < V Th , i.e. the MOS- FET remains in the cut-off region with i D = 0, regardless of

Voltage

v DS . The time interval (t 1 ,t 0 ) represents the delay turn-on time needed to change C GS from zero to V Th . The expression for

FIGURE 4.16 Variation of C gd and C gs as a function of v DS .

the time interval t 10 =t 1 −t 0 can be obtained as follows:

The gate current is given by,

In power electronics applications, the power MOSFETs are

v GG −v GS

operated at high frequencies in order to reduce the size of the

magnetic components. In order to reduce the switching losses, the power MOSFETs are maintained in either the on-state

=i C GS +i C GD

(conduction state) or the off-state (forward blocking) state. It is important we understand the internal device behav-

dv GS

d(v G −v D )

−C GD (4.13) ior; therefore, the parameters that govern the device transition

=C GS

dt from the on-state and off-states. To investigate the on and off switching characteristics, we consider the simple power where v G and v D are gate-to-ground and drain-to-ground electronic circuit shown in Fig. 4.17a under inductive load. voltages, respectively.

dt

4 The Power MOSFET 57 +V DD From Eqs. (4.13) and (4.14), we obtain,

V GG −v GS

dv GS = (C GS +C GD )

(4.15) R G dt

Solving Eq. (4.15) for v GS (t) for t > t 0 with v GS (t 0 ) = 0,

we obtain, i D

v GS (t ) =V GG (1

−e (t −t 0 )/τ ) (4.16)

(a)

i D (a)

v GG - GS S FIGURE 4.17 (a) Simplified equivalent circuit used to study turn-on

(b)

GS

v GG =V

- and turn-off characteristics of the MOSFET and (b) simplified equivalent

circuit.

(b)

FIGURE 4.18 Equivalent modes: (a) MOSFET is in the off-state for t<t 0 ,v GG = 0, v DS =V DD ,i G = 0, i D = 0; (b) MOSFET in the off-state with v GS < V Th for t 1 > t>t 0 ; (c) v GS > V Th ,i D < I 0 for t 1 < t<t 2 ; dv GS

Since we have v G =v GS ,v D = +V DD , then i G is given by

D =I 0 2 ≤t<t 3 GS

t 3 ≤t<t 4 .

58 I. Batarseh

V DD where,

τ =R G (C GS +C GD )

The gate current, i G , is given by,

v GG −v GS

G i C GD G (4.17)

e −(t−t 0 )/τ v

- As long as v GS < V Th ,i D remains zero. At t = t 1 ,v GS reaches

V Th causing the MOSFET to start conducting. Waveforms for (c)

i G and v GS are shown in Fig. 4.19. The time interval (t 1 −t 0 ) is

given by, +V DD

V Th t 10 =t 1 −t 0 = −τ ln 1 −