Solid-State Marx Generators

26.4.4 Solid-State Marx Generators

depending on that the capacitors are charged to the power sup- The use of voltage multiplication techniques for generating ply full voltage, V dc . During this time, the bottom impedances HV repetitive pulses is not limited to the use of transform- Z i limit the self-short-circuit path of the C i capacitors. ers. More complex methods can be used without the limitation

The circuit in Fig. 26.43 is assembled in such a way that there of transformers. The most common is the Marx generator is voltage modularity, meaning that each stage holds the power concept [55].

supply voltage V dc . However, due to this parallel process, the

26 Solid State Pulsed Power Electronics 697

0 FIGURE 26.43 t Marx generator topology for producing repetitive, nega- tive high-voltage pulses into a load.

t on

T (b)

first stages carry the total charging current, which sets different power requirements for the devices in each stage. ν 0

This concept has been used intensively through the years,

dc

with spark gaps used as switch S −nV

i for very high voltages and

powers, but the spark gap only turns off when the current

(c)

goes to zero. Recent technological upgrades with the addi- tion of solid-state switches and the replacement of most of the

passive elements increased the lifetime of the modulator and allowed higher pulse repetition rates, meaning an improved

FIGURE 26.45 Theoretic waveform for the operation of the circuit in

Fig. 26.44: (a) trigger signal of switches S pi ,v gs(Spi) ; (b) trigger signal of During the last years, various semiconductors based on Marx, switches S ci ,v gs(Sci) ; (c) output voltage, v 0 ; and (d) output current, i 0 . SM, and topologies have been described, with analogous char-

26.4.4.1 Generation of Negative Pulses

acteristics in order to reduce the losses and increase the per- Considering resistive load, R L , the operation of the Fig. 26.44 formance of the circuit for different types of applications and modulator can be understood considering two operating loads [56–59]. modes, for a switch duty ratio D =t on /T. In the first one, Figure 26.44 shows a typical SM topology, with n stages, able switches S ci and S pi are, respectively, turned on and turned off. to deliver negative high-voltage repetitive pulses into a load R L , During the charging period, (T −t on the theoretical key waveforms are shown in Fig. 26.45. Each ), capacitors C i are charged

from the dc charging power supply, V

dc , with current limited by

stage of the SM consists of a energy storing capacitor C ,a

the internal resistance of the semiconductors, wires, and the dc diode D ci , and two switches S ci and S pi , with antiparallel diodes, charging power supply internal resistance (or externally added) where the subscript i ∈ {1, 2, . . . , n−1, n, n+1}. The S i switches r , resulting in a small time constant that enables kHz opera- can be implemented with BJTs, GTOs, IGCTs, IGBTs, MOS-

dc tion. The on-state of D ci ensures that during this period, the

FETS, or other on–off devices. The inclusion of S c1 guarantees

voltage, v 0 , applied to the load is, approximately, zero. that during the pulse period, the dc charging power supply In the second operating mode, switches S ci and S pi are,

V dc is not short-circuited, preventing high current load pulses respectively, turn-off and turn-on. During the pulse mode, t on , through the power supply. capacitors C i are connected in series and their voltage applied

to the load. The load voltage v 0 is proportional to the charging

power supply S c1 S c2 S cn

r dc

v 0 = − knV dc , (26.32) +

V dc C C C C R ν 1 0 2 n −1 n L

where n is the number of stages, and k < 1 characterizes the

nonideal behavior of the passive and active elements in the S p1

S p2

S pn

circuit and operating conditions.

D c1 D c2 D The D ci diodes guarantee, also, that the S pi cn switches only block a maximum voltage of V dc , even in fault condition, such

FIGURE 26.44 Circuit for applying HV-negative repetitive pulses into as lack of synchronization. Considering Fig. 26.44, for example, resistive load.

if switch T pn is off during pulse mode, D cn conducts and short

698 L. Redondo and J. F. Silva

Assuming that V C i =V dc . Equating (26.38), the capacitor

c 0 value should satisfy the condition

Considering (26.34) through (26.39), it is mandatory to have storage energy greater than five times the pulse energy in order to have an output voltage droop better than 10%, but if a 1%

voltage droop is expected a 50 times storage energy is required, FIGURE 26.46 Equivalent circuit of Fig. 26.44: (a) the charging mode;

(a)

(b)

which impose limits to the design of the modulator. and (b) the pulse mode, for negative output pulses.

The power dissipation in the switches and the capacitors charging time impose a high-voltage pulse frequency limita-

circuits the last stage, imposing an output voltage of tion. Therefore, this circuit operates better with low duty ratio,

D, pulses as required in most PP applications.

v 0 = − k (n − 1) V dc .

In addition, the V dc power supply must be able to charge the

C i capacitors with an energy equal to the delivered pulse energy, The operation of Fig. 26.44 circuit can be represented by its E 0 , plus losses during the charging time, T −t on .

equivalent model during both operating modes, considering ideal switches and C i = C. During the charging mode, the C i

capacitors are in parallel, and the circuit can be modeled as

P V dc =

−P loss , (26.40)

T −t on

shown in Fig. 26.46a, where nC is the equivalent capacitance, seen by the power supply, charged with V dc . In addition, dur- where the P loss term represents the power dissipated in the ing pulse mode, the C i capacitors are in series, where C/n is the circuit wiring and switches.

This determines the maximum power rating for the V dc shown in Fig. 26.46b.

equivalent capacitance, seen by the load, charged with nV dc , as

power supply that imposes the maximum operating frequency, The energy stored in the C i capacitors, during T −t on , is

pulse duty ratio, and load power to the modulator.

2 To build and operate the circuit of Fig. 26.44, some design

E C i = CV ,

2 dc consideration must be considered. First, during start-up, when the energy storing capacitors are completely discharged, the

and the energy delivered to the load, during t on , is charging voltage V dc must be slowly increased in order to limit

2 V dc 2 the charging current on the switches S ci and D ci , which is crit-

E 0 =n

t on .

(26.35) ical in the first stages due to the parallel charging topology of

R L the capacitors.

For pulse power applications, only a small fraction of the Actually, in the parallel charging method, the semiconductor stored energy should be transferred to the output during the modules current loading is not equal. For instance, in Fig. 26.44 pulse mode; otherwise, the pulse voltage has a typical RC circuit, switch S c1 conducts current required to capacitors discharge waveform, not an almost rectangular shape. Consid- C 1 ,C 2 ,...,C n −1 ,C n , and switch S c2 conducts charging current ering a resistive load R L , the capacitance of the C i capacitors for C 2 ,C 3 ,...,C n −1 ,C n , and so forth. Thus, in practical imple- in the Fig. 26.44 circuit can be determined according to energy mentation, modules with successive decreasing current ratings delivered to the load. For the required pulse voltage droop,

can be used, the benefits of standardization being somewhat

V C f compromised.

Also, the S ci and S pi switches conduct different current

values, respectively, the discharge and pulse current. Hence, where V C f is the capacitors voltage at the end of pulse mode, instead of switches needing to block unequal voltages, they are

t on , and V C i is the capacitors voltage immediately before pulse required to conduct unequal currents. mode. Considering (26.36), the difference between (26.34) and

Consequently, when choosing semiconductors to implement (26.35) is the energy stored in the C i capacitors at end of pulse the S switches, it is fundamental that the semiconductor cur- mode, E C f ,

rent rating must be selected to guarantee that the devices work

(26.37) always in the saturation region inside the forward safe operat- where (26.37) for this case results in

E C i −E 0 =E C f ,

ing area. If not, during the first instants of the on-state (when the current is high), the semiconductors can operate in the

active region where the voltage drop and losses are higher,

t on =

2 which might destroy the devices.

26 Solid State Pulsed Power Electronics 699 The switches triggering is another important concern in

In order to guarantee the discharge of the load capaci- these circuits. There are two drive signals, v gs(Spi) and v gs(Sci) , tances after the negative HV pulse, it is necessary to change respectively, to S pi and S ci , which should be triggered syn- the Fig. 26.44 circuit topology for the one shown in Fig. 26.47, chronously. Since all the semiconductor switches are at dif- which also produces negative HV pulses into the load. ferent high-voltage potentials, gate-drive circuits with galvanic

Considering the circuit in Fig. 26.47, as the V dc power supply isolation are required (the use of optic fibers is mandatory to is negative, it is necessary to change the topology in compari- transmit the gate signals and to reduce stray capacitances to son with Fig. 26.44 in order to maintain a similar operating ground and neighbor cells), together with isolated power sup- behavior. The two main differences are the addition of an extra

plies to further process the transmitted gate signal and supply switch, S c0 , which guarantees that, during the pulse period, the power to the gate drivers.

dc charging power supply V dc does not participate in the pulse Several authors have come up with solutions to supply power mode, t on . The most important regards the fact that during the to semiconductor triggering drivers for high-voltage applica- charging period, T −t on , the S ci switches short circuit the load tions. The most common include isolation transformers [60], discharging any capacitance, as the one shown in Fig. 26.47. but diode strings are also described [58].

Considering now the application of negative HV pulses into The circuit in Fig. 26.44 enables the use of typical half- inductive loads, the circuit in Fig. 26.44 requires an additional bridge semiconductor structures currently integrated in mod- half-bridge switching structure that connects to the load, as ular packages, which is advantageous to assemble the circuit shown in Fig. 26.48. and trigger the semiconductors, since it allows bootstrap oper-

As shown in Fig. 26.49, the operation of the circuit ation [10].

in Fig. 26.48 in comparison with circuit in Fig. 26.44 as However, the circuit topology shown in Fig. 26.44 is not some changes, which includes one additional time period for suitable for dealing with capacitive loads. In fact, if a capacitive- enabling the reset of the inductive load by the freewheeling type load is connected to the circuit output, the load stays diodes, t ab , besides the charging, t c , and pulse modes, t on , in charged after the HV pulse with a negative voltage until the order to impose a zero average voltage to the load. charging mode of the energy storing capacitors. However,

During the charging period, the on-state of D ci and the during the charging period, the load is not shorted by the S p(n +1) antiparallel diode ensures that the output voltage, v 0 ,

D ci , except if the energy stored in the load is very low and applied to the load is approximately zero. the charging current of capacitors C i is sufficient to turn-on

After the HV-negative pulse, t on , the S ci and S pi switches diodes D ci .

are turned off, but in order to conserve energy, the inductive

FIGURE 26.47 Circuit for applying HV-negative repetitive pulses into a capacitive load, with a negative dc power supply, V dc .

FIGURE 26.48 Circuit for applying HV-negative repetitive pulses into an inductive load.

700 L. Redondo and J. F. Silva ν gs (S pi )

−nV dc A area A = area B

(c)

(d)

FIGURE 26.49 Theoretic waveform for the operation of the circuit in Fig. 26.48: (a) trigger signal of switches S pi ,v gs(Spi) ; (b) trigger signal of switches

S ci ,v gs(Sci) ; (c) output voltage, v 0 ; and (d) output current, i 0 .

load current, i 0 , must have an alternative path. This path is set charge the capacitors after each pulse is lower, and the yield of by freewheeling diodes (S ci antiparallel diodes and D ci diodes) this modulator can be higher. and the capacitor with the lowest voltage, which is charged.

E XAMPLE 26.9 A negative solid-state Marx generator Normally, C n has the lowest voltage, thus the current path is needs to be assembled for delivering

−9 kV, 25 µs pulses

through the S c(n +1) antiparallel diode D B , capacitor C n , and

diodes D c1 to D cn . During this time, t a , the voltage applied to

age droop. Considering the existent equipment, there the load is, about, V dc (voltage in capacitor C n ), resetting the are two alternatives as follows: (1) V inductive load. Capacitor C n is charged until its voltage is equal

dc = 1.5 kV, n = 6,

to the capacitor C n = 1 µF; (2) V dc = 1 kV, n = 9, and C i = 1 µF.

and C i

−1 voltage, after which, if there is still energy Determine which is the best alternative.

in the load, the current path changes to capacitor C n −1 . As the

S OLUTION . Considering the capacitance of 1 µs in each stages the longer the resetting time.

maximum clamping voltage is V dc , the higher the number of

stage, then the pulse voltage droop can be determined by In this way, most of the load magnetic energy is sent back

(26.39). Hence, for the first alternative to energy storing capacitors C i , after which the load current i 0 goes to zero and it can be imposed again the charging mode

0 ) to guarantee the completely reset of the load. Due to this load

of operation. It is important to have a safety time t b in order

R L (1

energy recovery method, the power supply energy needed to

26 Solid State Pulsed Power Electronics 701 and for the second alternative

connected in series and their voltage applied to the load. The

load voltage v 0 , is proportional to the charging power supply, 2nt on

where n is the number of stages, and k < 1 characterizes the nonideal behavior of the passive and active elements in the

which gives, respectively, 18.35% and 29.23% voltage circuit and operating conditions. Also, in this topology, for droop, meaning that after the pulse the capacitors stay

example, if S pn is off during pulse mode, the antiparallel S cn charged with about (26.36), respectively, 1224.7 and

diode conducts and short circuits the last stage, imposing an 707.1 V. Hence, only the first alternative keeps the pulse

output voltage of

voltage droop below 20%. In this case, the energy stored in the capacitors is (26.34) 6.75 J, three times bigger than

v 0 dc . (26.42) the energy delivered to the load during each pulse (26.35)

= k (n − 1) U

2.25 J. Actually, the Fig. 26.50 circuit is equivalent to Fig. 26.44 cir- cuit, whereas in this case, with a positive V dc power supply, it

can produce positive HV pulses for both resistive and capacitive The solid-state Marx modulators for generating positive HV loads. The capacitive load can be driven, given that during the

26.4.4.2 Generation of Positive Pulses

pulses, with different load conditions, have equivalent prop- charging mode of capacitors C i , the load is short circuited by erties as the ones for negative pulses, shown in the previ- the S ci switches, stray inductances limiting the discharge rate. ous section, besides the necessary modifications to enable the

Considering now the application of positive HV pulses into change in the output polarity. Thus, Fig. 26.50 shows the basic inductive loads, the circuit in Fig. 26.50 requires an additional

topology of the SM, with n stages, able to deliver positive high- switch S p0 and diode D 0 at the input, as shown in Fig. 26.51. voltage repetitive pulses into resistive and capacitive loads,

The circuit operation requires, also, an additional time R L C L .

period for resetting the inductive load by the added freewheel- During the pulse mode, t on , the switches S ci and S pi are, ing diodes, t ab , in addition to the charging, t c , and pulse modes,

respectively, turned off and turned on. Capacitors C i are t on , in order to impose a zero average voltage to the load.

FIGURE 26.50 Circuit for applying HV-positive repetitive pulses into resistive and capacitive loads.

FIGURE 26.51 Circuit for applying HV-positive repetitive pulses into an inductive load.

702 L. Redondo and J. F. Silva

Output FIGURE 26.52 Series switch for positive voltages based on the Marx concept.

Considering an inductive load, after the HV-positive pulse,

the S ci and S pi switches are off, and the path for the inductive current i r is set by the capacitor C , which usually has the low- dc

ν S1

est voltage, the S ci antiparallel diode and diode D B . During this

S dc C L

dc −V L voltage in capacitor C + n ), resetting the inductive load. After the

time, the voltage applied to the load is approximately ν (the C ν 0 R

V dc

load current i 0 goes to zero, the charging mode of operation can be imposed.

FIGURE 26.53 Proposed pulsed power HV topology for describing the

26.4.5 Solid-State Marx Based High-Voltage

operation of the series switch of Fig. 26.52.

Switches

The solid-state Marx generator concept described in the previ- conducting, S 1 holds off the voltage V dc . Hence, if the volt- ous section can be used for distributing the voltage in series- age V dc is greater than a couple of kilovolt, a solid-state switch stacked semiconductors. Further, the Marx generator circuit comprising series-stacked semiconductors is mandatory for

can be used as a series switch, maintaining some intrinsic prop- implementing switches S 1 and S 2 .

erties, which are desirable for the use with relatively low-voltage The switching frequency of S 1 and S 2 and the pulse on semiconductors, such as equal voltage distribution between time depend on the energy stored in the C dc capacitor, on the stages and the fact the semiconductors in each stage hold-off load consumption and on the power dissipated in the switches only the stage voltage capacitor.

during commutation.

The Marx series switch, based on the solid-state Marx of The proposed pulsed power topology in Fig. 26.53 imple- Fig. 26.50, for positive voltages, is shown in Fig. 26.52 not to mented with the series switch of Fig. 26.52 as series switch S 1 apply voltage but to hold it between its terminals. Therefore, (Marx 1) and S 2 (Marx 2) is shown in Fig. 26.54.

The operation of Fig. 26.54 circuit can be understood con- replaced by diodes D pi . Also, resistors R ci are connected in par- sidering the concept presented in Fig. 26.52 and the voltage allel with the D ci diodes in order to equalize the voltage in the waveforms presented in Fig. 26.56. For the first operating capacitors C i .

the input power supply V dc is removed and the S pi switches are

mode, during time t on , the S ci switches in Marx 1 are on, the C i

Consider the common HV pulse power topology of capacitors in Marx 1 are in parallel, and the S ci switches in Marx

Fig. 26.53, where switches S 1 and S 2 commutate alternately.

2 are off, as shown in Fig. 26.55a. The capacitor C dc voltage, v c ,

A HV power supply, V dc , charges an energy storage capacitor is applied into the load, v 0 , and the C i capacitors in Marx 2

C dc , with current limited by resistor R dc . The switch S 1 applies are stacked in series, through the D pi diodes, distributing the the capacitor C dc voltage v c to the capacitive load C L //R L , dur- voltage across the S ci switches, in parallel with the load.

Subsequently, in the second operating mode, during time load and other circuit parasitic capacitances to zero.

ing the pulse period, t on . Subsequently, switch S 2 discharges the

T −t on , the S ci switches in Marx 1 are off and the S ci switches in Taking into account the proposed operating scheme, each Marx 2 are on, and the load is discharged to zero, as shown in switch S i , where i ∈ {1, 2}, holds a maximum voltage equal Fig. 26.55b. The v c voltage appears between the Marx 1 termi- to the power supply voltage amplitude, V dc , considering that nals as shown in Fig. 26.56d, where this voltage is sustained by the capacitor C dc is charged with the voltage V dc . When S 1 the C i capacitors in series through the D pi diodes, distributing is conducting, S 2 holds off the voltage V dc , and when S 2 is the voltage across the S ci switches.

26 Solid State Pulsed Power Electronics 703

S 1 Marx 1

S c1 S 2 Marx 2

C 1 + FIGURE 26.54 Proposed pulsed power topology for testing the new series switches.

Unlike in a typical Marx generator, the C i capacitors in both for various load conditions. These topologies have in com- Marx 1 and Marx 2 of Fig. 26.54 can suffer from voltage imbal- mon the techniques for limiting the high-voltage stress onto ance problems due to the fact that the C i capacitors are charged the power semiconductor switches, still relatively low-voltage in series: (1) in Marx 1 during period T −t on , when the load is devices, considering the dozens of kilovolt needed for the

short-circuited and the voltage v C appears between the Marx 1 pulse power applications. Techniques spread from the series terminals, v S1 ; (2) in Marx 2 during period t on , when the volt- (and parallel) stacks of semiconductors switches, to generalized age is applied to the load and the voltage v C appears between cascodes, passing through the modified dc–dc isolated convert- the Marx 2 terminals.

ers for pulse generation, and their cascade association, to the Two main causes contribute to this voltage imbalance: (1) Marx-type solid-state generators topologies. the C i capacitances values are not equal; (2) the C i capacitors

With semiconductor-based generators, pulse power appli- placed near the V dc power supply are charged with a higher cations have expanded into many new fields such as mate- voltage due to the voltage droop in the semiconductors in each rial modification, environment protection, and biological and stage. Considering the later, the D ci diodes do not conduct medical developments. The presented topologies can bring a and R ci are used in parallel to uniformly distribute the voltage completely new extent of capability in repetition rate, effi- between the C i capacitors during: (1) t on in the Marx 1 switch; ciency, lifetime, compactness, and portability. (2) T −t on in Marx 2 switch. Alternatively, extra switches can

In addition to the methods to generate high-voltage pulse,

be placed in antiparallel with diodes D ci . the performances of the semiconductor switches determine the performance of the pulse power generators. In this way, power semiconductor devices have made significant progress

26.5 Conclusions and Future Trends

in both power capability and operation speed. Various semi- conductor switching units have become commercially avail-

This chapter reviewed some of the most typical semiconduc- able and have been used in various pulse power applications. tors and topologies used for generating repetitive unipolar and The most typical devices such as SOS diodes, GTOs, IGBTs bipolar high-voltage pulses based on semiconductor devices MOSFETs, and the emerging devices like SITh based on Si

704 L. Redondo and J. F. Silva

R c(n −1)

R c1

S 1 Marx 1

S c1 S 2 Marx 2

S Marx 1

S 2 Marx 2

ν S1 S cn

r dc

R c (n −1) +

c (n −1)

U dc C dc ν C ν 0 C n −1 +

R c1

S c1

C 1 + (b)

26 Solid State Pulsed Power Electronics 705

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