Space Charge Limiting Load (SCLL)

9.11 Space Charge Limiting Load (SCLL)

n + Using the concept of the space charge limited current flow, as shown in Fig. 9.22, it is possible to fabricate very large resis-

tors on a very small area. Moreover, these resistors have a FIGURE 9.22 Space charge limiting load (SCLL).

requires only several square micrometers when 2-µm feature size technology is used [7].

Depending on the value of the electrical field, the device cur- rent is described by the following two equations. For a small

9.12 Power MOS Transistors

electrical field v(x) = μE(x) Power MOS transistors are being used for fast switching power

I DS = V 2 DS A με Si ε 0 3 (9.16)

9 supplies and for switching power converters. They can be

driven with relatively small power, and switching frequencies could be very high. High switching frequencies lead to compact circuit implementations with small inductors and small capaci-

For a large electrical field v(x) = const tances. Basically, only two technologies, DMOS and VMOS, are

used for power MOS devices as shown in Figs. 9.23 and 9.24.

I DS = 2V DS v sat ε Si ε 0

A more popular structure is the DMOS shown in Fig. 9.24. This structure also uses the SIT concept. Note that for large drain voltages, the n-region is depleted from carriers and stati-

Moreover, these resistors, which are based on the space cally induced electrical field in the vicinity of the virtual drain is charge limit flow, have a very small parasitic capacitance.

significantly reduced. As a result, this transistor may withstand

9 Static Induction Devices 143 Source

Source

Poly gate

Source

Gate n +

Gate

Gate

Poly gate

FIGURE 9.23 Cross section of the VMOS transistor. C

PNP n +

Poly gate

Source

Poly gate

NPN

Drain

FIGURE 9.24 Cross section of the DMOS transistor.

(b)

FIGURE 9.26 Insulated gate bipolar transistor (IGBT): (a) cross section D and (b) equivalent diagram.

where its equivalent diagram consists of MOS transistor inte- grated with bipolar transistor. Such structure has β times larger transconductance (β is the current gain of bipolar transistor) and much smaller series resistance due to the conductivity modulation effect caused by holes injected into lightly doped

SIT

G MOS

drain region. Such device is known as insulated gate bipolar transistors (IGBT), which is shown in Fig. 9.26. Their main disadvantage is large switching time limited primarily by poor switching performance of bipolar transistor. Another difficulty is related to a possible latch-up action of four-layer n + pn − p +

structure. This undesired effect could be suppressed by using FIGURE 9.25 MOS and SIT equivalent to the structure of Fig. 9.24.

heavily doped p + region in the base of NPN structure, which leads to significant reduction of the current gain of this para- sitic transistor. The gain of other PNP transistor must be kept

much larger drain voltages and also the effect of channel length large, so the transconductance of the entire device is large too. modulation is significantly reduced. The later effect leads to The IGBT transistor has breakdown voltages up to 1500 V, and larger output resistances of the transistor. Therefore, the drain turn-off times are in the range 0.1–0.5 µs. They may oper- current is less sensitive to drain voltage variations. The struc- ate with currents above 100 A with a forward voltage drop of ture shown in Fig. 9.24 can be considered a composition of the about 3 V. MOS transistor and the SIT transistor as shown in Fig. 9.25.

The major disadvantage of power MOS transistors is rela- tively large drain series resistance and much smaller transcon-

9.13 Static Induction Thyristor

ductance in comparison to bipolar transistors. Both of these parameters can be improved dramatically by a simple change There are several special semiconductor devices dedicated of the type of drain, in the case of n-channel device from n-type to high-power applications. The most popular is thyristor to p-type drain. This way the integrated structure is being built known also as silicon control rectifier (SCR). This device is

144 B. M. Wilamowski Anode

Anode

pnp

n + Gate

C Gate

npn

Cathode

(b) FIGURE 9.29 Integrated structure of silicon control rectifier: (a) cross

(a)

Cathode

section and (b) equivalent diagram.

(a)

(b)

FIGURE 9.27 Silicon control rectifier: (a) cross section and (b) equiva- lent diagram.

Anode

pnp Anode

C Cathode

(b) Gate

npn

(a)

FIGURE 9.30 GTO-SIT: (a) cross section and (b) equivalent diagram.

FIGURE 9.28 Silicon control rectifier with larger dv/dt parameter: The classical thyristor shown in Fig. 9.27 can be turned off by (a) cross section and (b) equivalent diagram.

the gate voltage while integrated SCR shown in Fig. 9.29 can be only turned off by decreasing anode current to zero. Most of the SCRs sold in the market have an integrated structure composed of two or more thyristors. This structure has both large dv/dt

a four-layer structure as shown in Fig. 9.27a and it can be and di/dt parameters. considered as two transistors npn and pnp connected as shown in Fig. 9.27b.

In normal operation mode (anode has positive potential), only one junction is reverse-biased, and it can be represented

9.14 Gate Turn-Off Thyristor

by capacitance C. A spike of anode voltage can, therefore, be obtained through capacitor C, and it can trigger SCR. This For dc operation, it is important to have a thyristor that can behavior is not acceptable in practical applications and there-

be turned off by the gate voltage. Such thyristor has a structure fore a different device structure is being used as shown in similar to the one shown in Fig. 9.27. However, it is important

Fig. 9.28. Note that by shorting gate to cathode by resistor R, to have significantly different current gains β for pnp and npn it is much more difficult to trigger the npn transistor by spike transistors. The current gain of npn transistor should be as large of anode voltage. This way rapid change of anode voltages is as possible, and the current gain of pnp transistor should be not able to trigger thyristor. Therefore, this structure has very small. The product of β npn and β pnp should be larger than one. large dv/dt parameter.

This can be easily implemented using SI structure as shown in When NPN transistor is replaced with SItransistor, parame- Fig. 9.30. ters of a thyristor can be significantly improved. For example,

with breaking voltage in the range of 5 kV and current of 600 A, the switching on time can be as short as 100 ns and dv/dt

9.15 Summary

parameter can be as large as 50 kV/s [16, 25]. Most of the SCRs sold in the market comprise an integrated Several devices from the static induction family such as static structure composed of two or more thyristors. This structure induction transistor (SIT), static induction diode (SID), static has both large dv/dt and di/dt parameters. This structure con- induction thyristor, lateral punch-through transistor (LPTT), sists of internal thyristor that significantly amplifies the gate static induction transistor logic (SITL), static induction MOS signal.

transistor (SIMOS), and space charge limiting load (SCLL) are

9 Static Induction Devices 145 described. The theory of operation of static induction devices

12. J. Nishizawa, T. Ohmi, and H. L. Chen, “Analysis of Static Characteris- is given for both a current controlled by a potential barrier and

tics of a Bipolar-Mode SIT (BSIT),” IEEE Trans. Electron Devices, vol.

a current controlled by space charge. The new concept of a

29, No. 8, pp. 1233–1244, August 1982.

punch-through emitter (PTE), which operates with majority 13. K. Yano, I. Henmi, M. Kasuga, and A. Shimizu, “High-Power Rectifier carrier transport, is presented.

Using the BSIT Operation,” IEEE Trans. Electron Devices, vol. 45, No.

2, pp. 563–565, February 1998. 14. K. Yano, M. Masahito, H. Moroshima, J. Morita, M. Kasuga, and A. Shimizu, “Rectifier Characteristics Based on Bipolar-Mode SIT

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