DC–DC Isolated Converters opposite secondary transformer terminal. The auxiliary RCD

26.4.2 DC–DC Isolated Converters opposite secondary transformer terminal. The auxiliary RCD

voltage clamp circuit connected to the transformer primary The use of classic high-voltage modulator topologies, such as the ones described in the previous section, substituting the hard-tube switches by stacked semiconductors is frequently

N 1 :N 2 D 2 not the best solution for high-voltage pulse generation when

− ka + using semiconductors, due to the still high-voltage limitations

of the devices and their sensibility to over-voltage and over- v 1 v 2 R L ν 0 currents. −

− − Alternatively, it is advantageous to take into account the

+ r dc + C

topologies that were originally designed for power semicon- ductors such as the dc–dc isolated converters. The literature

refers the use of full-bridge, half-bridge, forward and flyback

V dc +

converters in hard-switching and resonant topologies for appli-

v ka

+ cations such as rapid capacitor high-voltage charging, food

v processing, X-ray, plasma processing, and air and water pol- ds lution control [32–35]. −

The use of a transformer for galvanic isolation in the forward converter, derived from the buck dc–dc converter, the flyback converter, derived from the buck-boost dc–dc converter, and FIGURE 26.30 Simplified layout of the pulsed power forward-type cir- the bridge topologies can significantly reduce the voltage stress cuit used to generate negative, high-voltage pulses to a load.

688 L. Redondo and J. F. Silva t

on

off

applied to the load is

v gs(S)

V dc ,

where N 2 /N 1 is the transformer turns ratio, N. In addition, the v

(a)

RCD diode D 1 is off, with a reverse voltage of

1 A area = B area

A V dc B v ka(D 1 ) =V dc +V C . (26.13)

−V C For a resistive load R L , the pulse amplitude is given by

In the second mode, the reset mode, when the main switch S

V dc +V C V dc turns off, the RCD diode D

1 goes on and the voltage applied to

transformer primary winding is

−V C , which resets the trans-

2 T, the secondary diode D 2 is v ka (D 2)

(c)

off, holding off a reverse voltage of

V /N

v ka(D 2 ) =

V C , (26.15)

(d)

v which results into a zero-load voltage. From (26.15), the lower

ka (D1)

the V C voltage and the transformer turns ratio N , the lower is the voltage hold-off by diode D 2 . In addition, the switch S must

V dc +V C V C

hold-off a voltage

(e)

v s =V dc +V C , (26.16) v 0

−V dc N 2 /N 1 where V C must be as low as possible to decrease this voltage. Finally, in the third mode, the safety mode, following the

3 T, still with S off, the

(f)

voltage applied to S is

FIGURE 26.31 Theoretical key waveforms for the circuit in Fig. 26.30, for a resistive load: (a) switch-trigger signal v gs ; (b) primary winding volt-

(26.17) age, v 1 ; (c) switch voltage v s ; (d) D

=V

dc ,

2 reverse voltage; (e) D 1 reverse voltage;

and (f) load voltage v 0 . and the voltage applied to the transformer is zero. It is impor-

3 T > 0 in order to guarantee a safety operating margin for the transformer core reset. For practical opera- tion, values between 20% and 30% should be sufficient. This is

winding is used to reset the transformer using the lowest con- done by increasing the V C clamp voltage above the calculated stant voltage. Considering that the RCD clamp capacitance C s

value. is sufficiently large, the voltage V C across it can be assumed

The operation of Fig. 26.30 circuit for high-voltage pulse constant [48, 49]. generation imposes several conditions as follows: For pulse generation, the circuit operation can be explained

considering only three operating modes [32, 50]. In the first

1. The use of a step-up transformer in order to decrease mode, the pulse mode, when the main switch S is turned on

the voltage on the devices connected on the primary

1 T = DT = t on , where D and T are, respectively, the

side;

S duty ratio and operating period, the energy is transferred

2. A minimum reset voltage V C to guarantee the complete from the transformer primary winding circuit to the output. As

3 T>

the voltage applied to the transformer primary winding N 1 is

0, reducing at the same time the hold-off voltage of D 2

V dc , the secondary winding N 2 diode D 2 is on, thus the voltage

(26.15) and of S (26.16).

26 Solid State Pulsed Power Electronics 689 Considering the second condition, it is important to under-

stand the relation between the reset voltage V C with the

operating conditions, such as the duty ratio D.

The reset voltage V C can be calculated by equating the inte-

V 0 /|

gral of the primary winding voltage, v 1

1 , over one time period

ka

to zero

FIGURE 26.32 Graphic representation of the reverse voltage of diode

D 2 + as a function of the reset time and duty ratio of the forward topology

Various conditions can be presented for high-voltage pulse

generation by forward converters using low-voltage solid-state devices as follows:

2 T = τ is the transformer core reset period.

2 T =T

1. If the switching duty ratio is only a few percent, and the

2 = D), (26.18) becomes resetting time extends to almost all the main switch-

3 T), diode D 2 holds off a small

V dc .

fraction of the output voltage;

1 −D

2. If a step-up transformer is used, N ≫ 1, this topology enables, also, the use of low hold-off voltage semicon-

Substituting (26.19) in (26.15) results for v ka in diode D 2 results

ductors in the primary transformer side, when com- in pared with the output load voltage.

V ka(D2) =

V C V dc .

For safety reasons in order to ensure that the transformer N 1 = N 1 2 core is fully reset, the transformer resetting time must end

3 T > 0. Considering (26.18) and (26.20) and introducing the load The short duty cycles required for generation of HV pulses voltage module |V 0 | and the ratio of τ /t off , the reset time and with low-voltage semiconductors is not a shortcoming, as most the time switch S is off, results in PP applications require short-pulse widths and large recovery

V ka(D2) t on

Much care should be put in the design and assembling of

the transformer as this element must sustain the HV between DT

t off

its terminals. In addition, this topology requires the polar- = 2 T

(26.21) ity of the primary winding of the transformer to be identical t off ( T −t on )

to that of the secondary winding and so the energy of the load is obtained during the on-state of the switching device.

Simplifying (26.21) becomes Therefore, it behaves like a true transformer, wherein energy storage is undesirable, associated with the leakage inductance.

V ka

(26.22) However, the forward converter transformers have the poorest

|V 0 | τ t off ( 1 − D)

utilization and efficiency ratios, because neither the core nor the windings are used during the lengthy core reset interval.

which can be represented graphically by Fig. 26.32, where Due to the low, main switch S duty-cycle operation and transformer behavior, the RCD clamp voltage is designed for a

(26.23) = low current, typically, a few percent of the main circuit current. ) t = off 2 3 T 2 3 The RCD clamp can be considered a buck-boost converter in discontinuous mode of operation, and designed so that,

under any load conditions, during the S switch-off period, the The graphic in Fig. 26.32 shows the maximum load voltage transformer core is fully reset [49]. hold-off by diode D 2 as a function of S duty ratio, D, and the

1 2 3 1 = D.

For resetting the transformer core, other solutions can be transformer reset factor, τ /t off .

implementing, such as a third auxiliary winding, but the fact

690 L. Redondo and J. F. Silva that this transformer is for HV pulse generation, limits in terms

N 1 :N 2 D 2 of parasitic, assembling complexity and safety.

E + XAMPLE 26.6 Suppose the generation of −5 kV ampli- v 1 v 2

v ka

= 10 kHz (D = 5%) from the R L tude pulses with 5 µs and f ν 0

circuit in Fig. 26.30. The circuit is supplied from a mains −

transformer at V dc = 500 V and a N = 10 pulse trans-

r dc + C

former is used. Calculate the semiconductor switches S,

1 , and D 2 hold-off voltage.

V dc +

OLUTION . Consider first boundary condition (26.19),

The semiconductors hold-off at 526.3 V for the S switch

FIGURE 26.33 Simplified layout of the pulsed power flyback-type cir- 10.5% and 5.26% of the output voltage.

and diode D 1 , and 263 V for diode D 2 , respectively,

cuit used to generate negative high-voltage pulses to a load. Consider now a reset factor of τ /t off ≈ 65%, then

1 2 3 ≈ 32.5%. From (26.18)

When the main switch S is turned off, the energy stored in the

t on

transformer is transferred to the output. The voltage applied

V C =V dc

= 40 V,

to the transformer primary winding is −V C ; the RCD diode

D 1 and the secondary winding diode D 2 are on, and voltage

resulting in 540 V for the S switch and diode D 1 , and

applied to the load is, approximately,

400 V for diode D 2 , respectively, 10.8% and 8% of the output voltage.

V C . (26.26) Hence, for generating 5-kV pulse, 800 V semiconduc-

v 0 =−

tors could be used, considering a 100% safety factor. The voltage hold-off the main switch S is

v ds =V dc +V C . (26.27)

26.4.2.2 Flyback Topology

The simplified flyback-type circuit used to generate negative The RCD clamp voltage has two purposes: (1) reduce the high-voltage pulses into a load is shown in Fig. 26.33; for voltage spike that occurs due to the resonance between the positive pulses, the ground should be placed on the opposite transformer leakage inductance and the switch S output capac- terminal.

itance, in the off state; and (2) establish the pulse voltage during The circuit in Fig. 26.33 is similar to the circuit shown in the same period of time.

Considering the transformer primary winding voltage wave- winding is reversed. However, this simple change imposes form given in Fig. 26.34, the clamp voltage, V C , can be approxi- completely different circuit behavior [48].

Fig. 26.30, but the polarity of the diode D 2 on the secondary

mately derived by equating the integral of the primary winding Considering the circuit in Fig. 26.33 and the theoretical key voltage, v 1 , over one time period to zero waveforms of Fig. 26.34, for boundary conditions, when the main switch S turns on, the energy is stored in the transformer

V dc , (26.28) as magnetic flux, the transformer must act as a coil storing

1 −D

energy. The voltage applied to the transformer primary wind- ing is V

dc ; the RCD diode D 1 and the secondary winding diode

similar to the V C

voltage in the buck-boost topology (26.19).

D 2 are off, thus the voltage applied to the load is zero. The Concerning high-voltage pulse generation [50], if the secondary diode D reverse voltage is

switching duty ratio is near 100%, D 2 blocks only a small frac-

2 tion of the output voltage. Additionally, if the RCD diode D

N 2 is on during the S switch-off time, meaning the flyback cir-

v ka(D 2 ) =

V dc ,

N 1 cuit runs in continuous mode, the output voltage pulse is well defined by the RCD capacitors voltage V C . Moreover, with

and the RCD diode D 1 reverse voltage is

a step-up transformer (N ≫ 1), this topology also enables relatively low-voltage semiconductor devices in the primary

v ka(D 1 ) =V dc +V C .

(26.25) side.

26 Solid State Pulsed Power Electronics 691 v gs (S )

during the off state of the S switch, meaning that the trans- V i

former must be designed to store energy during the on state of the S switch, behaving as a coupled inductor.

The S switch current interruption requirements and the cou-

t on T

pled inductor design can be much more challenging in the

flyback topology at power levels of interest and represent a lim- v 1

(a)

itation of this topology. This is normally the realm of much V A

higher current devices such as the IGBT and GTO or the use of

dc

parallel semiconductors.

B Nevertheless, the flyback circuit is much more fault tolerant −V C

A area = B area

to a short circuit in the load or load faults since the switch S

(b)

is in the off state during the output pulse and will not see the fault current as would the forward converter topology.

v ds Comparing the forward and flyback topologies for HV pulse V dc +V C

generation for the same output voltage pulse amplitude, using the same turn ratio transformer, the forward circuits need a

high amplitude dc PS voltage V dc , but the RCD voltage is lower

and the switch S duty ratio is low. Also, in the flyback topology,

the voltage pulse width is not as well defined as in the forward v ka (D 2)

(c)

because it is generated by the RCD circuit. Both topologies have problems in dealing with capacitive

N 2 V loads because the dynamic variations in the load impedance N dc 1 mismatch the output of the transformer. The solution requires

the use of a permanent dummy load, but this increases the

power dissipation. Another possibility is the use of a switch

dummy load, which will put a semiconductor device in the v ka (D1)

(d)

high-voltage region.

V dc +V C

E XAMPLE 26.7 Suppose the generation of −5 kV ampli- tude pulses with 5 µs and f = 10 kHz (D = 95%) from the circuit in Fig. 26.33. The circuit is supplied at V dc = 25 V

and a N = 10 pulse transformer is used. Calculate the

(e)

semiconductor switches S, D 1 , and D 2 hold-off voltage. v 0 S OLUTION . Consider (26.28), then

The semiconductors hold-off at 526.3 V for the S switch FIGURE 26.34 Theoretical key waveforms for the circuit in Fig. 26.33,

(f)

and diode D 1 , and 263 V for diode D 2 , respectively, for a resistive load: (a) switch-trigger signal v gs ; (b) primary winding volt-

10.5% and 5.26% of the output voltage.

Hence, for generating 5-kV pulse, 800 V semiconduc- and (f) load voltage v 0 .

age, v 1 ; (c) switch voltage v s ; (d) D 2 reverse voltage; (e) D 1 reverse voltage;

tors could be used, considering a 100% safety factor.

For efficiency reasons, the flyback circuit parameters should

26.4.2.3 Bridge Topologies

be calculated in order that the circuit works at the boundary The forward and flyback topologies are suitable for the genera- between the continuous and noncontinuous state. This is done tion of unipolar HV pulses. If bipolar pulses are needed, bridge by assuring that the RCD diode D 1 turns off at the same instant configurations should be used, like the full- and half-bridge the switch S turning on. The RCD clamp voltage is sized by the topologies with or without a step-up transformer [32–35]. main circuit current due to the high duty ratio operation of

Considering a half-bridge topology (Fig. 26.35a) shows the switch S and the coil-like transformer behavior.

configuration for obtaining positive pulses, where the switch The flyback transformer design is more complex than the S 1 applies the pulse to the load, and switch S 2 is capable of forward transformer, as the energy is supplied to the load applying a zero voltage to the load, which can be important

692 L. Redondo and J. F. Silva if the load is capacitive, as shown in Fig. 26.35b, otherwise, the must hold-off the sum of the two power supplies voltages, that

load will stay charged. If antiparallel diodes are connected to is, 2V dc . However, for capacitive-type loads, it is not possible the switches, pulses can be applied to inductive loads, where the to discharge the load capacitance after the pulse, as shown in S 2 antiparallel diode reset the load after the pulse. For negative Fig. 26.37b, since both S 1 and S 2 must be off. pulses, the circuit is presented in Fig. 26.36a, similar operat-

In order to decrease the switches voltage hold-off, it is com- ing behavior applies now for opposite polarity, as shown in mon to use the full-bridge topology, shown in Fig. 26.38a, Fig. 26.36b.

which also uses one less power supply. Each switch hold-off The main limitation of this topology is the hold-off voltage voltage is only V dc . The use of more switches also increases of the semiconductors, which must block the same voltage as the capability to deal with different load conditions, as shown the dc HV power supply V dc . If a transformer is connected in in Fig. 26.38b. In fact, with the full-bridge topology, positive parallel with switch S 2 , its antiparallel diode can reset the trans- and/or negative pulses can be applied to any type of load. Nev- former core after the pulse, but this is limited to low duty ratio ertheless, depending on the flux of energy not all the controlled operation due to the low-reset voltage impose by the diode.

turn-off switches are always required. If positive and negative pulses (i.e., bipolar) need to be gen-

These topologies are used in applications such as rapid high- erated using a half-bridge topology, then two power supplies voltage capacitor charging, food processing, or air pollution are required, as shown in Fig. 26.37. In this case, each switch S i control, where bipolar pulses enhance the process [26–30].

FIGURE 26.35 Half-bridge topology for generating positive HV pulses; (a) simplified circuit and (b) output voltage, v 0 , for a capacitive load, C L //R L .

FIGURE 26.36 Half-bridge topology for generating negative HV pulses; (a) simplified circuit and (b) output voltage, v 0 , for a capacitive load, C L //R L .

FIGURE 26.37 Half-bridge topology for generating positive and/or negative HV pulses; (a) simplified circuit and (b) output voltage, v 0 , for a capacitive load, C L //R L .

26 Solid State Pulsed Power Electronics 693

FIGURE 26.38 Full-bridge topology for generating positive and/or negative HV pulses; (a) simplified circuit and (b) output voltage, v 0 , for a capacitive load, C L //R L .

It is also possible to connect a transformer at the output ter-

minals to increase the output voltage amplitude and to lower i 0 the hold-off voltage in the semiconductors switches if high-

voltage pulses are to be generated, with the limitations already

described. In order to limit the switches losses, it is common to use auxiliary inductors and capacitors in series or parallel con- R 2

figurations to couple the H-bridge to the HV transformer and also to guarantee a zero average voltage applied to the primary S 2

C 2 D 2 + winding. R L ν 0