C HAPTER T HREE L OGI C C ON CEPT S
C HAPTER T HREE L OGI C C ON CEPT S
Science when well digested is nothing but good sense and reason.
—Leszinski Stanislas
Industrial Text & Video Company 1-800-752-8398
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S ECTION Introductory Logic C HAPTER 1 Concepts
Concepts 3
C HAPTER To understand programmable controllers and their applications, you must
H IGHLIGHTS first understand the logic concepts behind them. In this chapter, we will discuss three basic logic functions—AND, OR, and NOT—and show you how, with just these three functions, you can make control decisions ranging from very simple to very complex. We will also introduce you to the fundamentals of Boolean algebra and its associated operators. Finally, we will explain the relationship between Boolean algebra and logic contact symbology, so that you will be ready to learn about PLC processors and their programming devices.
3 -1 T HE B I N A RY C ONCEPT
The binary concept is not a new idea; in fact, it is a very old one. It simply refers to the idea that many things exist only in two predetermined states. For instance, a light can be on or off, a switch open or closed, or a motor running or stopped. In digital systems, these two-state conditions can be thought of as signals that are present or not present, activated or not activated, high or low, on or off, etc. This two-state concept can be the basis for making decisions; and since it is very adaptable to the binary number system, it is a fundamental building block for programmable controllers and digital computers.
Here, and throughout this book, binary 1 represents the presence of a signal (or the occurrence of some event), while binary 0 represents the absence of the signal (or the nonoccurrence of the event). In digital systems, these two states are actually represented by two distinct voltage levels, +V and 0V, as shown in Table 3-1. One voltage is more positive (or at a higher reference) than the other. Often, binary 1 (or logic 1) is referred to as TRUE, ON, or HIGH, while binary 0 (or logic 0) is referred to as FALSE, OFF, or LOW.
O p e r a t i n g N o t o p e r a t i n g L i m i t s w i t c h R i n g i n g N o t r i n g i n g B e ll
B l o w i n g S li e n t
V a l v e Table 3-1. Binary concept using positive logic.
Note that in Table 3-1, the more positive voltage (represented as logic 1) and the less positive voltage (represented as logic 0) were arbitrarily chosen. The use of binary logic to represent the more positive voltage level, meaning the occurrence of some event, as 1 is referred to as positive logic.
Industrial Text & Video Company 1-800-752-8398
www.industrialtext.com
S ECTION Introductory Logic C HAPTER 1 Concepts
Concepts 3
Negative logic , as illustrated in Table 3-2, uses 0 to represent the more positive voltage level, or the occurrence of the event. Consequently, 1 represents the nonoccurrence of the event, or the less positive voltage level. Although positive logic is the more conventional of the two, negative logic is sometimes more convenient in an application.
N o t o p e r a t i n g O p e r a t i n g L i m i t s w i t c h N o t r i n g i n g R i n g i n g B e ll
S li e n t
C l o s e d V a l v e Table 3-2. Binary concept using negative logic.
Parts
» An Industrial Text Company Publication Atlanta • Georgia • USA
» C HAPTER T HREE L OGI C C ON CEPT S
» 3 -3 P RINCIPLES OF B OOLEAN A LGEBRA AND L OGIC
» 3 -4 PLC C I RCU I T S AN D L OGI C C ON TACT S Y M BOLOGY
» C ONTACT S YMBOLS U SED IN PLC S
» L OADING C O N S I D E R AT I O N S
» M E M O RY C A PA C I T Y AND U T I L I Z AT I O N
» A P P L I C AT I O N M E M O RY
» D AT A T ABLE O R G A N I Z AT I O N
» 6 -2 I /O R ACK E NCLOSURES AND T ABLE M APPING
» I /O R ACK AND T ABLE M APPING E XAMPLE
» 6 -4 P L C I NSTRUCTIONS FOR D ISCRETE I NPUTS
» 6 -6 P L C I NSTRUCTIONS F OR D ISCRETE O UTPUTS
» 7 -3 A NALOG I NPUT D ATA R E P R E S E N TAT I O N
» 7 -4 A NALOG I NPUT D ATA H ANDLING
» 7 -6 O V E RV I E W OF A NALOG O UTPUT S IGNALS
» 7 -8 A NALOG O UTPUT D ATA R E P R E S E N TAT I O N
» 7 -9 A NALOG O UTPUT D ATA H ANDLING
» C HAPTER E IGHT S PECI AL F U N CT I ON I /O AN D S ERI AL C OM M U N I CAT I ON I N T ERFACI N G
» T HERMOCOUPLE I NPUT M ODULES
» E NCODER /C OUNTER I N T E R FA C E S
» S TEPPER M OTOR I N T E R FA C E S
» S ERVO M OTOR I N T E R FA C E S
» N ETWORK I N T E R FA C E M ODULES
» S ERIAL C O M M U N I C AT I O N
» I N T E R FA C E U SES AND A P P L I C AT I O N S
» 9 -3 L ADDER D IAGRAM F O R M AT
» 9 -5 L ADDER R E L AY P ROGRAMMING L ADDER S CAN E V A L U AT I O N
» P ROGRAMMING N O R M A L LY C LOSED I NPUTS
» 9 -1 0 A RITHMETIC I NSTRUCTIONS
» 9 -1 4 N ETWORK C O M M U N I C AT I O N I NSTRUCTIONS
» L ANGUAGES AND I NSTRUCTIONS
» F UNCTION B LOCK D IAGRAM (FBD)
» S EQUENTIAL F UNCTION C H A RT S (SFC)
» P ROGRAMMING L ANGUAGE N O TAT I O N
» P ROGRAMMING N O R M A L LY C LOSED T RANSITIONS
» D IVERGENCES AND C ONVERGENCES
» -1 C ONTROL T ASK D EFINITION
» C REAT I N G F LOWCH ART S AN D O U T PU T S EQU EN CES
» C ONFIGURING THE PLC S YSTEM
» S PECIAL I NPUT D EVICE P ROGRAMMING
» S IMPLE S TA R T /S TOP M OTOR C IRCUIT
» F O RWA R D /R EVERSE M OTOR I NTERLOCKING
» AC M OTOR D RIVE I N T E R FA C E
» L ARGE R E L AY S YSTEM M O D E R N I Z AT I O N
» A NALOG I NPUT C OMPARISON AND D ATA L INEARIZATION
» A NALOG P OSITION R EADING F ROM AN LV D T
» L INEAR I N T E R P O L AT I O N OF N ONLINEAR I NPUTS
» L ARGE B AT C H I N G C ONTROL A P P L I C AT I O N
» -7 S H O RT P ROGRAMMING E XAMPLES
» -1 B ASIC M EASUREMENT C ONCEPTS D ATA I N T E R P R E TAT I O N
» I NTERPRETING C OMBINED E RRORS
» B RIDGE C IRCUIT T ECHNIQUES
» R ESISTANCE T E M P E R AT U R E D ETECTORS ( RT D S )
» -1 P ROCESS C ONTROL B ASICS
» I N T E R P R E TAT I O N OF E RROR
» T RAN SFER F U N CT I ON S AN D T RAN SI EN T R ESPON SES
» D E R I V AT I V E L APLACE T RANSFORMS
» Out () s = ( )( ) In () s Hp () s
» S ECOND -O RDER L AG R ESPONSES
» D IRECT -A CTING C ONTROLLERS
» T WO -P OSITION D ISCRETE C ONTROLLERS
» T HREE -P OSITION D ISCRETE C ONTROLLERS
» -5 P R O P O RT I O N A L C ONTROLLERS (P M ODE )
» PV () s ( 1 + Hc Hp () s () s ) = SP Hc Hp () s () s () s
» CV () t = K I ∫ 0 Edt + CV ( t = 0 )
» CV ( t = 2 ) = K I 0 Edt + ∫ CV ( t = 1 )
» -7 P R O P O RT I O N A L -I NTEGRAL C ONTROLLERS (PI M ODE )
» -8 D E R I VAT I V E C ONTROLLERS (D M ODE ) S TANDARD D E R I V AT I V E C ONTROLLERS
» -9 P R O P O RT I O N A L -D E R I VAT I V E C ONTROLLERS (PD M ODE )
» -1 2 C ONTROLLER L OOP T UNING
» Z IEGLER –N ICHOLS O PEN -L OOP T UNING M ETHOD
» I TA E O PEN -L OOP T UNING M ETHOD
» S O F T WA R E T UNING M ETHODS
» R ULE -B ASED K NOWLEDGE R E P R E S E N T AT I O N
» S T AT I S T I C A L AND P ROBABILITY A N A LY S I S
» -1 I NTRODUCTION TO F UZZY L OGIC
» -2 H I S T O RY OF F UZZY L OGIC
» -3 F UZZY L OGIC O P E R AT I O N
» F U Z Z I F I C AT I O N C OMPONENTS
» F UZZY P ROCESSING C OMPONENTS
» D E F U Z Z I F I C AT I O N C OMPONENTS
» S YSTEM D ESCRIPTION AND O P E R AT I O N
» M EMBERSHIP F UNCTIONS AND R ULE C R E AT I O N
» IF A = PS AND B = NS THEN C = ZR IF A = PS AND B = NS THEN D = NS
» C HAPTER N INETEEN I /O B US N ET WORK S
» -4 D EVICE B US N ETWORKS B YTE -W IDE D EVICE B US N ETWORKS
» B IT -W IDE D EVICE B US N ETWORKS
» F IELDBUS P ROCESS B US N ETWORK
» P ROFIBUS P ROCESS B US N ETWORK
» I /O B US N ETWORK A DDRESSING
» P ANEL E NCLOSURES AND S YSTEM C OMPONENTS
» -3 N OISE , H E AT , AND V O LTA G E R EQUIREMENTS
» T ROUBLESHOOTING PLC I NPUTS
» -2 P L C S IZES AND S COPES OF A P P L I C AT I O N S
» I NPUT /O UTPUT C O N S I D E R AT I O N S
» C ONTROL S YSTEM O R G A N I Z AT I O N
» E Q U I VA L E N T L ADDER /L OGIC D IAGRAMS
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