P ROGRAMMING L ANGUAGE N O TAT I O N

As we have noted, sequential function charts can provide the infrastructure for a control program, which is then built using one or more of the four IEC 1131-3 programming languages. In the next section, we will further explain how SFCs can be used implement a control program. However, let’s first review the similarities between programming notations in the ladder diagram (LD), function block diagram (FBD), structured text (ST), and instruction list (IL) languages.

Figure 10-19 shows a simple ladder diagram and its FBD, ST, and IL language equivalents. Note that the ST language (see Figure 10-19c) uses two operators, AND and &, to denote the AND function. The := symbol is used in an ST program to assign an output variable (e.g., Valve_3) to a logic expression. In instruction list (see Figure 10-19d), the first instruction (instruction LD) loads the status of variable Limit_S_1 to the accumulator register, which IL calls the result register. The second instruction (instruction AND) ANDs the status of Limit_S_1 with the variable Start_Cycle and stores the outcome back in the result register. The third instruction (instruction ST) stores the contents of the result register as the output variable, Valve_3. This process is similar to Boolean programming language.

As demonstrated, the instructions used to implement control sequences in each programming language are very similar in their construction, as well as their visual representation. Depending on the PLC application, an SFC may use one or more of these languages to program instructions inside its actions. To differentiate between languages, some software manufacturers include starting and ending commands that define the language being used. Other manufacturers allow the mixing of languages without any differentiation between them. Figure 10-20 illustrates a group of instructions that have been labeled with a differentiation mnemonic. The term #Language=name signals the beginning of a language, and #ENDlanguagename signals the end of it.

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S ECTION PLC The IEC 1131 Standard and C HAPTER 3 Programming

Programming Language 10

Bool_Var (Boolean variable) Inputs:

Limit_S_1 for Limit Switch 1 Start_Cycle for Start Cycle PB

Bool_Var (Boolean variable) Outputs:

Valve_3 for Solenoid Valve #3

Inputs

Output

Limit_S_1 Start_Cycle

Valve_3

(a) Ladder diagram (LD) (a) Ladder diagram (LD)

Limit_S_1

AND

Valve_3

Start_Cycle

(b) Function block diagram (FBD) (b) Function block diagram (FBD)

Input

Output

Logic Expression

Valve_3:=Limit_S_1 AND Start_Cycle or Valve_3:=Limit_S_1 & Start_Cycle

Inputs and Outputs

Control Logic

Name Variable

Description

(*Load the status of Limit_S_1*)—variable to the result register AND Start_Cycle (*AND it with Start_Cycle*)—variable ANDed with result register ST

Limit_S_1

Valve_3

(*Result register is stored as the Boolean variable Valve_3*)

(d) Instruction list (IL) (d) Instruction list (IL)

Figure 10-19. Implementation of a simple program in (a) ladder diagram, (b) function block diagram, (c) structured text, and (d) instruction list.

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S ECTION PLC The IEC 1131 Standard and C HAPTER 3 Programming

Programming Language 10

#Language=LD

#ENDlanguageLD #Language=ST

If Motor Then Light_Out Else DL_Motor_Off

#ENDlanguageST #Language=FBD

b & OR

LS #ENDlanguageFBD

#Language=IL LD LS1

AND LS2 STR Motor

#ENDlanguageIL

Figure 10-20. Languages within an SFC differentiated by beginning and ending

language labels.

E X AM PLE 1 0 -3

In PLC applications, many limit switches exhibit a “bouncing” behavior (see Figure 10-21), meaning that the switch opens and closes several times before finally turning ON or OFF. Develop an encapsulated custom function block (see Figure 10-22), which will provide 50 msec debouncing capabilities, that can be stored in a library and used to program all bouncing input limit switches. Note that debouncing must be performed for both the OFF-to-ON and the ON- to-OFF transitions.

S OLU T I ON

Figure 10-23 illustrates the timing diagram of the limit switch input. It shows that a 50 msec delay (shown in blue) should exist in the OFF- to-ON and ON-to-OFF transitions to filter any bouncing signals. Timers can be used to implement both delays.

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S ECTION PLC The IEC 1131 Standard and C HAPTER 3 Programming

Programming Language 10

Bouncing may cause a faulty reading

Figure 10-21. Bouncing behavior in a limit switch.

Input Wiring

PLC Program

LS_Before Debounce FBD Valid_LS DB OUT

Figure 10-22. Rough diagram of an encapsulated debouncing function block.

1 LS_Before

50 msec

Valid_LS 50 msec

DT: Delay Time

Delays to prevent false triggering of signal

Figure 10-23. Timing diagram for a bouncing input signal. Figure 10-24 illustrates the implementation of a debouncing circuit

using ladder diagrams and an ON-delay energize timer. Figure 10-25 shows the corresponding timing diagram. Note that the output of the latch/unlatch output (102) is the actual input, in this case the limit

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S ECTION PLC The IEC 1131 Standard and C HAPTER 3 Programming

Programming Language 10

Debounce FBD

Valid_LS

LS_Before

OUT 102

(Latch/Unlatch) Preset

ACC

Inputs

Delay_Time Reg

Reg

LS_Before: The input to

the block from the limit

switch before debouncing. Preset Reg 4100: The reg-

ister that holds the delay constant defined by the

LS_Before

TON 100

user’s input named De- lay_Time, in this case 50

LS_Before

TON 101

OUT 102: The FBD output of the limit switch after the

AR 4001

debounce delay.

PR 4100

ACC Reg: Registers 4000

Valid_LS

and 4001, which hold the

L102

value of the timer’s accu-

mulated registers.

Valid_LS

U102

Figure 10-24. Debouncing function block programmed using ladder diagram.

LS_Before

1 DT Set

0 50 msec

LS_Before

1 DT

Reset

DT 50 msec

1 DT Valid_LS

0 50 msec

Figure 10-25. Timing diagram for the ladder circuit in Figure 10-24. switch signal after passing through the debouncing circuit. Figure 10-

26 illustrates the same type of debouncing filter implementation using FBD. Note that the output of the set/reset (S/R), or bistable, block will

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S ECTION PLC The IEC 1131 Standard and C HAPTER 3 Programming

Programming Language 10

also be the debounced limit switch input (Valid_LS). The variable T_Delay will be an integer that is a preset time value of 50 msec. The input signals LS_Before (limit switch before debouncing) and Valid_LS (limit switch after debouncing) are both Bool (TRUE/FALSE) variables. Once created, the function block diagram can be encapsulated as a custom block as shown in Figure 10-27a. It can then be used with any input that requires a 50 msec debounce filter (see Figure 10- 27b). The encapsulated block can satisfy any debounce requirement as long as the T_Delay variable is specified accordingly.

LS_Before

Valid_LS

TON_2 IN OUT

50 msec

T_Delay

Figure 10-26. Debouncing circuit programmed using FBD. Three limit switches—

LS1, LS2, and LS3— defined as: LS1_Before, LS2_Before, and LS3_Before.

Debounce

Debouce FBD

LS1_Before

Block

LS_Before

Valid_LS

Valid_LS1

LS_Before OUT

T_Delay

LS2_Before

Valid_LS2 IN OUT

T_Delay

LS3_Before

Valid_LS3 IN OUT

T_Delay

(b)

Figure 10-27. (a) FBD as an encapsulated custom block and (b) a custom block used

to debounce three limit switch signals.

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S ECTION PLC The IEC 1131 Standard and C HAPTER 3 Programming

Programming Language 10

P ROGRAMMING L ANGUAGE N O TAT I O N