E RROR C HECKING

E RROR C HECKING

The processor uses error-checking techniques to monitor the functional status of both the memory and the communication links between subsystems and peripherals, as well as its own operation. Common error-checking techniques include parity and checksum.

Parity. Parity is perhaps the most common error detection technique. It is used primarily in communication link applications to detect mistakes in long, error-prone data transmission lines. The communication between the CPU and subsystems is a prime example of the useful application of parity error checking. Parity check is often called vertical redundancy check (VRC).

Parity uses the number of 1s in a binary word to check the validity of data transmission. There are two types of parity checks: even parity, which checks for an even number of 1s, and odd parity, which checks for an odd number of 1s. When data is transmitted through a PLC, it is sent in binary format, using 1s and 0s. The number of 1s can be either odd or even, depending on the character or data being transmitted (see Figure 4-16a). In parity data transmis- sion, an extra bit is added to the binary word, generally in the most significant or least significant bit position (see Figure 4-16b). This extra bit, called the parity bit (P), is used to make each byte or word have an odd or even number of 1s, depending on the type of parity being used.

Even 1s

Parity → P 1011 0110 1000 1010

Even 1s

Figure 4-16. (a)

A 16-bit data transmission of 1s and 0s and (b) the same transmission with a parity bit (P) in the most significant bit position.

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Let’s suppose that a processor transmits the 7-bit ASCII character C (1000011) to a peripheral device and odd parity is required. The total number of 1s is three, or odd. If the parity bit (P) is the most significant bit, the transmitted data will be P1000011. To achieve odd parity, P is set to 0 to obtain an odd number of 1s. The receiving end detects an error if the data does not contain an odd number of 1s. If even parity had been the error-checking method, P would have been set to 1 to obtain an even number of 1s.

Parity error checking is a single-error detection method. If one bit of data in

a word changes, an error will be detected due to the change in the bit pattern. However, if two bits change value, the number of 1s will be changed back, and an error will not be detected even though there is a mistransmission.

In PLCs, when data is transmitted to a subsystem, the controller defines the type of parity (odd or even) that will be used. However, if the data transmission is from the programmable controller to a peripheral, the parity method must be prespecified and must be the same for both devices.

Some processors do not use parity when transmitting information, although their peripherals may require it. In this case, parity generation can be accomplished through application software. The parity bit can be set for odd or even parity with a short routine using functional blocks or a high-level language. If a nonparity-oriented processor receives data that contains parity,

a software routine can also be used to mask out, or strip, the parity bit. Checksum. The extra bit of data added to each word when using parity error

detection is often too wasteful to be desirable. In data storage, for example, error detection is desirable, but storing one extra bit for every eight bits means

a 12.5% loss of data storage capacity. For this reason, a data block error- checking method known as checksum is used.

Checksum error detection spots errors in blocks of many words, instead of in individual words as parity does. Checksum analyzes all of the words in a data block and then adds to the end of the block one word that reflects a characteristic of the block. Figure 4-17 shows this last word, known as the block check character (BCC) . This type of error checking is appropriate for memory checks and is usually done at power-up.

There are several methods of checksum computation, with the three most common being:

• cyclic redundancy check • longitudinal redundancy check • cyclic exclusive-OR checksum

Cyclic Redundancy Check. Cyclic redundancy check (CRC) is a technique that performs an addition of all the words in the data block and then stores the resulting sum in the last location, the block check character (BCC). This

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Word 1 Word 2 Word 3

Last Word Figure 4-17. Checksum Block check character at the end

of the data block.

summation process can rapidly reach an overflow condition, so one variation of CRC allows the sum to overflow, storing only the remainder bits in the BCC word. Typically, the resulting word is complemented and written in the BCC location. During the error check, all words in the block are added together, with the addition of the final BCC word turning the result to 0. A zero sum indicates a valid block. Another type of CRC generates the BCC using the remainder of dividing the sum by a preset binary number.

Longitudinal Redundancy Check. Longitudinal redundancy check (LRC)

is an error-checking technique based on the accumulation of the result of performing an exclusive-OR (XOR) on each of the words in the data block. The exclusive-OR operation is similar to the standard OR logic operation (see Chapter 3) except that, with two inputs, only one can be ON (1) for the output to be 1. If both logic inputs are 1, then the output will be 0. The exclusive-OR

operation is represented by the ⊕ symbol. Figure 4-18 illustrates the truth table for the exclusive-OR operation. Thus, the LRC operation is simply the

logical exclusive-OR of the first word with the second word, the result with the third word, and so on. The final exclusive-OR operation is stored at the end of the block as the BCC.

Exclusive-OR Truth Table

Figure 4-18. Truth table for the exclusive-

OR operation.

Cyclic Exclusive-OR Checksum. Cyclic exclusive-OR checksum (CX-

ORC) is similar to LRC with some slight variations. The operation starts with

a checksum word containing 0s, which is XORed with the first word of the block. This is followed by a left rotation of the bits in the checksum word. The next word in the data block is XORed with the checksum word and then

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rotated left (see Figure 4-19). This procedure is repeated until the last word of the block has been logically operated on. The checksum word is then appended to the block to become the BCC.

A software routine in the executive program performs most checksum error- detecting methods. Typically, the processor performs the checksum compu- tation on memory at power-up and also during the transmission of data. Some controllers perform the checksum on memory during the execution of the control program. This continuous on-line error checking lessens the possibil- ity of the processor using invalid data.

Bit 7 6 5 4 3 2 1 0

Data Before Data 1 0 1 1 0 1 0 1 Rotation

1 Data During 0 1 1 0 1 0 1 Rotation

Bit 7 Rotates to Bit 0 Position

Data After 0 1 1 0 1 0 1 1 Rotation

Figure 4-19. Cyclic exclusive-OR checksum operation.

E X AM PLE 4 -3

Implement a checksum utilizing (a) LRC and (b) CX-ORC techniques for the four, 6-bit words shown. Place the BCC at the end of the data block.

(a) Longitudinal redundancy check:

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LRC data block:

(b) Cyclic exclusive-OR check: Start with checksum word 000000.

CS start

left rotate

left rotate

left rotate

left rotate

1 0 0 1 0 0 (final checksum)

CX-ORC data block:

Error Detection and Correction. More sophisticated programmable con- trollers may have an error detection and correction scheme that provides greater reliability than conventional error detection. The key to this type of error correction is the multiple representation of the same value.

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The most common error-detecting and error-correcting code is the Hamming code . This code relies on parity bits interspersed with data bits in a data word. By combining the parity and data bits according to a strict set of parity equations, a small byte is generated that contains a value that identifies the erroneous bit. An error can be detected and corrected if any bit is changed by any value. The hardware used to generate and check Hamming codes is quite complex and essentially implements a set of error-correcting equations.

Error-correcting codes offer the advantage of being able to detect two or more bit errors; however, they can only correct one-bit errors. They also present a disadvantage because they are bit wasteful. Nevertheless, this scheme will continue to be used with data communication in hierarchical systems that are unmanned, sophisticated, and automatic.