ATM ROUTING AND CONCENTRATION CHIP

THE ABACUS SWITCH 208 Fig. 7.14 Block diagram of the ARC chip.

7.5 ATM ROUTING AND CONCENTRATION CHIP

Ž . An application-specific integrated circuit ASIC has been implemented based on the abacus switch architecture. Figure 7.14 shows the ARC chip’s block diagram. Each block’s function and design are explained briefly in the w x following sections. Details can be found in 3 . The ARC chip contains 32 = 32 SWEs, which are partitioned into eight SWE arrays, each with w x 32 = 4 SWEs. A set of input data signals, w 0 : 31 , comes from the IPCs. w x Another set of input data signals, n 0 : 31 , either comes from the output, w x s 0 : 31 , of the chips on the above row, or is tied to high for the chips on the Ž . w x first row in the multicast case . A set of the output signals, s 0 : 31 , either go to the north input of the chips one row below or go to the output buffer. A signal x is broadcast to all SWEs to initialize each SWE to across state, where the west input passes to the east and the north input passes to the Ž . south. A signal x specifies the address bit s used for routing cells, while x 1 2 specifies the priority field. Other output signals x propagate along with cells to the adjacent chips on the east or south side. w x Signals m 0 : 1 are used to configure the chip into four different group Ž . Ž . sizes as shown in Table 7.1: 1 eight groups, each with 4 output links, 2 four Ž . groups, each with 8 output links, 3 two groups, each with 16 output links, Ž . w x and 4 one group with 32 output links. A signal m 2 is used to configure the TABLE 7.1 Truth Table for Different Operation Modes a w x w x m 1 m 0 Operation 8 groups with 4 links per group 1 4 groups with 8 links per group 1 2 groups with 16 links per group 1 1 1 group with 32 links per group a w x w x m 2 s 1 multicast, m 2 s 0 unicast. ATM ROUTING AND CONCENTRATION CHIP 209 Fig. 7.15 32 = 4 SWE array. w x chip to either unicast or multicast application. For the unicast case, m 2 is w x set to 0, while for the multicast case, m 2 is set to 1. As shown in Figure 7.15, the SWEs are arranged in a crossbar structure, where signals only communicate between adjacent SWEs, easing the synchro- nization problem. ATM cells are propagated in the SWE array similarly to a wave propagating diagonally toward the bottom right corner. The signals x 1 and x are applied from the top left of the SWE array, and each SWE 2 distributes them to its east and south neighbors. This requires the same phase of the signal arriving at each SWE. x and x are passed to the 1 2 Ž . neighbor SWEs east and south after one clock cycle delay, as are the data Ž . Ž signals w and n . A signal x is broadcast to all SWEs not shown in Figure . 7.15 to precharge an internal node in the SWE in every cell cycle. The output signal x is used to identify the address bit position of the cells in 1 e the first SWE array of the next adjacent chip. The timing diagram of the SWE input signal and its two possible states are shown in Fig. 7.16. Two bit-aligned cells, one from the west and one from the north, are applied to the SWE along with the signals dx and dx , which 1 2 determine the address and priority fields of the input cells. The SWE has two states: cross and toggle. Initially, the SWE is initialized to a cross state by the signal dx , i.e., cells from the north side are routed to the south side, and cells from the west side are routed to the east side. When the address Ž . of the cell from the west dw is matched with the address of the cell from a Ž . Ž . the north dn , and when the west’s priority level dw is higher than the a p Ž . north’s dn , the SWEs is toggled. The cell from the west side is then routed p THE ABACUS SWITCH 210 Fig. 7.16 Two states of the switch element. to the south side, and the cell from the north is routed to the east. Otherwise, the SWE remains at the cross state. The 32 = 32 ARC chip has been designed and fabricated using 0.8-␮m CMOS technology with a die size of 6.6 mm = 6.6 mm. Note that this chip is pad-limited. The chip has been tested successfully up to 240 MHz, and its characteristics are summarized in Table 7.2. Its photograph is shown in Figure 7.17. TABLE 7.2 Chip Summary Process technology 0.8-␮m CMOS, triple metal Number of switching elements 32 = 32 Configurable group size 4, 8, 16, or 32 output links Pin count 145 Package Ceramic PGA Number of transistors 81,000 2 Die size 6.6 = 6.6 mm Clock signals Pseudo ECL Interface signals TTLrCMOS inputs, CMOS outputs Maximum clock speed 240 MHz Worst case power dissipation 2.8 W at 240 MHz ENHANCED ABACUS SWITCH