ATM ROUTING AND CONCENTRATION CHIP
7.5 ATM ROUTING AND CONCENTRATION CHIP
Ž . An application-specific integrated circuit ASIC has been implemented based on the abacus switch architecture. Figure 7.14 shows the ARC chip’s block diagram. Each block’s function and design are explained briefly in the w x following sections. Details can be found in 3 . The ARC chip contains 32 = 32 SWEs, which are partitioned into eight SWE arrays, each with w x 32 = 4 SWEs. A set of input data signals, w 0 : 31 , comes from the IPCs. w x Another set of input data signals, n 0 : 31 , either comes from the output, w x s 0 : 31 , of the chips on the above row, or is tied to high for the chips on the Ž . w x first row in the multicast case . A set of the output signals, s 0 : 31 , either go to the north input of the chips one row below or go to the output buffer. A signal x is broadcast to all SWEs to initialize each SWE to across state, where the west input passes to the east and the north input passes to the Ž . south. A signal x specifies the address bit s used for routing cells, while x 1 2 specifies the priority field. Other output signals x propagate along with cells to the adjacent chips on the east or south side. w x Signals m 0 : 1 are used to configure the chip into four different group Ž . Ž . sizes as shown in Table 7.1: 1 eight groups, each with 4 output links, 2 four Ž . groups, each with 8 output links, 3 two groups, each with 16 output links, Ž . w x and 4 one group with 32 output links. A signal m 2 is used to configure the TABLE 7.1 Truth Table for Different Operation Modes a w x w x m 1 m 0 Operation 8 groups with 4 links per group 1 4 groups with 8 links per group 1 2 groups with 16 links per group 1 1 1 group with 32 links per group a w x w x m 2 s 1 multicast, m 2 s 0 unicast. ATM ROUTING AND CONCENTRATION CHIP 209 Fig. 7.15 32 = 4 SWE array. w x chip to either unicast or multicast application. For the unicast case, m 2 is w x set to 0, while for the multicast case, m 2 is set to 1. As shown in Figure 7.15, the SWEs are arranged in a crossbar structure, where signals only communicate between adjacent SWEs, easing the synchro- nization problem. ATM cells are propagated in the SWE array similarly to a wave propagating diagonally toward the bottom right corner. The signals x 1 and x are applied from the top left of the SWE array, and each SWE 2 distributes them to its east and south neighbors. This requires the same phase of the signal arriving at each SWE. x and x are passed to the 1 2 Ž . neighbor SWEs east and south after one clock cycle delay, as are the data Ž . Ž signals w and n . A signal x is broadcast to all SWEs not shown in Figure . 7.15 to precharge an internal node in the SWE in every cell cycle. The output signal x is used to identify the address bit position of the cells in 1 e the first SWE array of the next adjacent chip. The timing diagram of the SWE input signal and its two possible states are shown in Fig. 7.16. Two bit-aligned cells, one from the west and one from the north, are applied to the SWE along with the signals dx and dx , which 1 2 determine the address and priority fields of the input cells. The SWE has two states: cross and toggle. Initially, the SWE is initialized to a cross state by the signal dx , i.e., cells from the north side are routed to the south side, and cells from the west side are routed to the east side. When the address Ž . of the cell from the west dw is matched with the address of the cell from a Ž . Ž . the north dn , and when the west’s priority level dw is higher than the a p Ž . north’s dn , the SWEs is toggled. The cell from the west side is then routed p THE ABACUS SWITCH 210 Fig. 7.16 Two states of the switch element. to the south side, and the cell from the north is routed to the east. Otherwise, the SWE remains at the cross state. The 32 = 32 ARC chip has been designed and fabricated using 0.8-m CMOS technology with a die size of 6.6 mm = 6.6 mm. Note that this chip is pad-limited. The chip has been tested successfully up to 240 MHz, and its characteristics are summarized in Table 7.2. Its photograph is shown in Figure 7.17. TABLE 7.2 Chip Summary Process technology 0.8-m CMOS, triple metal Number of switching elements 32 = 32 Configurable group size 4, 8, 16, or 32 output links Pin count 145 Package Ceramic PGA Number of transistors 81,000 2 Die size 6.6 = 6.6 mm Clock signals Pseudo ECL Interface signals TTLrCMOS inputs, CMOS outputs Maximum clock speed 240 MHz Worst case power dissipation 2.8 W at 240 MHz ENHANCED ABACUS SWITCHParts
» ATM Switch Structure ATM SWITCH SYSTEMS
» DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
» Internal Link Blocking Output Port Contention Head-of-Line Blocking
» Shared-Medium Switch Time-Division Switching
» Single-Path Switches Space-Division Switching
» Multiple-Path Switches Space-Division Switching
» Internally Buffered Switches Recirculation Buffered Switches
» Input- and Output-Buffered Switches Virtual-Output-Queueing Switches
» Input-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Completely Shared-Buffer Switches PERFORMANCE OF BASIC SWITCHES
» Bernoulli Arrival Process and Random Traffic On–Off Model and Bursty Traffic
» Multiline Input Smoothing Speedup Parallel Switch
» Window-Based Lookahead Selection Increasing Scheduling Efficiency
» VOQ-Based Matching Increasing Scheduling Efficiency
» Parallel Iterative Matching PIM Iterative Round-Robin Matching iRRM
» Iterative Round-Robin with SLIP i SLIP
» Dual Round-Robin Matching DRRM
» Round-Robin Greedy Scheduling SCHEDULING ALGORITHMS
» Bidirectional Arbiter Design of Round-Robin Arbiters r
» Token Tunneling This section introduces a more efficient arbi-
» Most-Urgent-Cell-First Algorithm MUCFA OUTPUT-QUEUING EMULATION
» Critical Cell First CCF Last In, Highest Priority LIHP
» LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST JONATHAN CHAO CHEUK LAM
» LINKED LIST APPROACH JONATHAN CHAO CHEUK LAM
» CONTENT-ADDRESSABLE MEMORY APPROACH JONATHAN CHAO CHEUK LAM
» Washington University Gigabit Switch
» Shared-Memory Switch with a Multicast Logical Queue Shared-Memory Switch with Cell Copy
» Shared-Memory Switch with Address Copy
» BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
» Three-Phase Implementation Ring Reservation
» BATCHER-SORTING NETWORK THE SUNSHINE SWITCH
» Tandem Banyan Switch DEFLECTION ROUTING
» Shuffle-Exchange Network with Deflection Routing
» Dual Shuffle-Exchange Network with Error-Correcting Routing
» Generalized Self-Routing Algorithm Broadcast Banyan Network
» Boolean Interval Splitting Algorithm Nonblocking Condition of Broadcast Banyan Networks A
» Encoding Process MULTICAST COPY NETWORKS
» Concentration Decoding Process Overflow and Call Splitting
» A. Cyclic Running Adder Network Figure 5.34 shows the struc-
» Concentration The starting point in a CRAN may not be port 0,
» Basic Architecture SINGLE-STAGE KNOCKOUT SWITCH
» Knockout Concentration Principle SINGLE-STAGE KNOCKOUT SWITCH
» Construction of the Concentrator
» Maximum Throughput CHANNEL GROUPING PRINCIPLE
» Two-Stage Configuration A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Multicast Grouping Network A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Translation Tables A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Cross-Stuck CS Fault Toggle-Stuck TS Fault Verticalr
» Toggle-Stuck and Cross-Stuck Cases
» Vertical-Stuck and Horizontal-Stuck Cases
» Cross-Stuck and Toggle-Stuck Cases
» Vertical-Stuck Case Horizontal-Stuck SWE Case
» APPENDIX JONATHAN CHAO CHEUK LAM
» BASIC ARCHITECTURE JONATHAN CHAO CHEUK LAM
» MULTICAST CONTENTION RESOLUTION ALGORITHM
» IMPLEMENTATION OF INPUT PORT CONTROLLER
» Cell Loss Probability PERFORMANCE
» ATM ROUTING AND CONCENTRATION CHIP
» Memoryless Multistage Concentration Network
» Buffered Multistage Concentration Network
» Resequencing Cells ENHANCED ABACUS SWITCH
» Complexity Comparison ENHANCED ABACUS SWITCH
» Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» Cell Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» MSDA Structure MULTIPLE-QOS SDA SWITCH
» OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES OVERVIEW OF INPUT
» Basic Architecture Unicasting Operation
» ROUTING PROPERTIES AND SCHEDULING METHODS
» A SUBOPTIMAL STRAIGHT MATCHING METHOD
» Basic Architecture Distributed and Random Arbitration
» Basic Architecture THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
» Concurrent Round-Robin Dispatching Scheme
» Homogeneous Capacity and Route Assignment
» The Staggering Switch ALL-OPTICAL PACKET SWITCHES
» HYPASS OPTOELECTRONIC PACKET SWITCHES
» STAR-TRACK OPTOELECTRONIC PACKET SWITCHES
» Cisneros and Brackett’s Architecture
» Basic Architecture THE 3M SWITCH
» Cell Delineation Unit THE 3M SWITCH
» VCI-Overwrite Unit Cell Synchronization Unit
» Input and Output Forwarding Engines Input and Output Switch Interfaces
» Route Controller Router Module and Route Controller
» Input Optical Module Output Optical Module Tunable Filters
» Principles of Ping-Pong Arbitration Consider an N-input
» Performance of PPA Implementation of PPA
» Priority PPA Ping-Pong Arbitration Unit
» Component Complexity OIN Complexity
» Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
» Crosstalk Analysis OPTICAL INTERCONNECTION NETWORK FOR
» System Considerations WIRELESS ATM STRUCTURE OVERVIEWS
» NEC’s WATMnet Prototype System
» Olivetti’s Radio ATM LAN Virtual Connection Tree
» BAHAMA Wireless ATM LAN NTT’s Wireless ATM Access
» Radio Physical Layer RADIO ACCESS LAYERS
» Medium Access Control Layer Data Link Control Layer
» Connection Rerouting HANDOFF IN WIRELESS ATM
» Buffering Cell Routing in a COS
» Design of a Mobility-Support Switch
» Performance MOBILITY-SUPPORT ATM SWITCH
» Architectures of Generic Routers
» IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE IP ROUTE LOOKUP BASED ON STANDARD
» Levels 2 and 3 of Data Structure
» Adapting Binary Search for Best-Matching Prefix
» Precomputed 16-Bit Prefix Table Multiway Binary Search: Exploiting the Cache Line
» Lookup Algorithms and Data Structure Construction
» Prefix Update Algorithms IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
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