IP Route Lookup Algorithm
13.9.1 IP Route Lookup Algorithm
Ž . In this subsection, we will illustrate how to do IP lookups. The IPLookup X algorithm is shown below. The input of the function is the IP destination address X of an incoming packet, which is in the dotted decimal form. The function returns the next hop of the longest matching prefix found in the two-trie structure. Algorithm IPLookup X 1. Let Z be the variable that stores the next hop of the longest matching prefix. Initially Z is the default next hop. 2. Start to do an IP lookup from the root node of the front trie by matching each K-bit part of the destination address X of the packet with prefixes in the two-trie structure. 3. If there is a match, the traversal is moved to the child node at the next level of the front trie. IP ROUTE LOOKUPS 398 4. Whenever a new front node is arrived at, the algorithm first looks for Ž its child node corresponding to the symbol 噛 which must be the . separate node . If the node is found, it means that the two-trie structure contains a longer matching prefix, so the variable Z is updated with the next hop value of this prefix retrieved from the separate node. 5. When the separate node is reached, matching continues to the rear Ž trie by using a pointer at the separate node shown as a dashed line . in Fig. 13.29 . Matching on the rear trie is done in the backward direction. 6. The algorithm stops whenever Ž . Ž a a mismatch is detected somewhere in the structure in such a case, . the current value of Z is returned as the next hop , or Ž . Ž b the traversal reaches the root node of the rear trie no mismatch is . detected . This means that the destination address X of the packet is actually stored as a prefix in the structure. The variable Z is updated with the next hop value of the prefix stored at the separate node we previously visited and returned as the output of the function. Suppose that we would like to look up the destination address X s ² : 130.44.64.71.噛 from the two-trie structure shown in Figure 13.29. The lookup starts from the root node of the front trie and proceeds along the front trie by moving to the next nodes 6 and 12. Then, the traversal is transferred to the rear trie and continues through the rear nodes 7, 6, and 1 until the root node of the rear trie is reached. The algorithm stops, and the next hop stored at the separate node 12 is assigned to the variable Z and returned as the output. Note that the algorithm can be improved by keeping track of the number of parts of the address X it has already matched. Instead of traversing until reaching the root node of the rear trie, in this example the algorithm can stop when 71, which is the last part of X, is matched at the rear node 6. ² : Now let us change the destination address X to 130.44.64.72.噛 and do the lookup again. When the traversal is at the rear node 6, there is no match with 72. The algorithm stops and returns the current value Z, which is the default next hop, as the output.13.9.2 Prefix Update Algorithms
Parts
» ATM Switch Structure ATM SWITCH SYSTEMS
» DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
» Internal Link Blocking Output Port Contention Head-of-Line Blocking
» Shared-Medium Switch Time-Division Switching
» Single-Path Switches Space-Division Switching
» Multiple-Path Switches Space-Division Switching
» Internally Buffered Switches Recirculation Buffered Switches
» Input- and Output-Buffered Switches Virtual-Output-Queueing Switches
» Input-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Completely Shared-Buffer Switches PERFORMANCE OF BASIC SWITCHES
» Bernoulli Arrival Process and Random Traffic On–Off Model and Bursty Traffic
» Multiline Input Smoothing Speedup Parallel Switch
» Window-Based Lookahead Selection Increasing Scheduling Efficiency
» VOQ-Based Matching Increasing Scheduling Efficiency
» Parallel Iterative Matching PIM Iterative Round-Robin Matching iRRM
» Iterative Round-Robin with SLIP i SLIP
» Dual Round-Robin Matching DRRM
» Round-Robin Greedy Scheduling SCHEDULING ALGORITHMS
» Bidirectional Arbiter Design of Round-Robin Arbiters r
» Token Tunneling This section introduces a more efficient arbi-
» Most-Urgent-Cell-First Algorithm MUCFA OUTPUT-QUEUING EMULATION
» Critical Cell First CCF Last In, Highest Priority LIHP
» LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST JONATHAN CHAO CHEUK LAM
» LINKED LIST APPROACH JONATHAN CHAO CHEUK LAM
» CONTENT-ADDRESSABLE MEMORY APPROACH JONATHAN CHAO CHEUK LAM
» Washington University Gigabit Switch
» Shared-Memory Switch with a Multicast Logical Queue Shared-Memory Switch with Cell Copy
» Shared-Memory Switch with Address Copy
» BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
» Three-Phase Implementation Ring Reservation
» BATCHER-SORTING NETWORK THE SUNSHINE SWITCH
» Tandem Banyan Switch DEFLECTION ROUTING
» Shuffle-Exchange Network with Deflection Routing
» Dual Shuffle-Exchange Network with Error-Correcting Routing
» Generalized Self-Routing Algorithm Broadcast Banyan Network
» Boolean Interval Splitting Algorithm Nonblocking Condition of Broadcast Banyan Networks A
» Encoding Process MULTICAST COPY NETWORKS
» Concentration Decoding Process Overflow and Call Splitting
» A. Cyclic Running Adder Network Figure 5.34 shows the struc-
» Concentration The starting point in a CRAN may not be port 0,
» Basic Architecture SINGLE-STAGE KNOCKOUT SWITCH
» Knockout Concentration Principle SINGLE-STAGE KNOCKOUT SWITCH
» Construction of the Concentrator
» Maximum Throughput CHANNEL GROUPING PRINCIPLE
» Two-Stage Configuration A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Multicast Grouping Network A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Translation Tables A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Cross-Stuck CS Fault Toggle-Stuck TS Fault Verticalr
» Toggle-Stuck and Cross-Stuck Cases
» Vertical-Stuck and Horizontal-Stuck Cases
» Cross-Stuck and Toggle-Stuck Cases
» Vertical-Stuck Case Horizontal-Stuck SWE Case
» APPENDIX JONATHAN CHAO CHEUK LAM
» BASIC ARCHITECTURE JONATHAN CHAO CHEUK LAM
» MULTICAST CONTENTION RESOLUTION ALGORITHM
» IMPLEMENTATION OF INPUT PORT CONTROLLER
» Cell Loss Probability PERFORMANCE
» ATM ROUTING AND CONCENTRATION CHIP
» Memoryless Multistage Concentration Network
» Buffered Multistage Concentration Network
» Resequencing Cells ENHANCED ABACUS SWITCH
» Complexity Comparison ENHANCED ABACUS SWITCH
» Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» Cell Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» MSDA Structure MULTIPLE-QOS SDA SWITCH
» OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES OVERVIEW OF INPUT
» Basic Architecture Unicasting Operation
» ROUTING PROPERTIES AND SCHEDULING METHODS
» A SUBOPTIMAL STRAIGHT MATCHING METHOD
» Basic Architecture Distributed and Random Arbitration
» Basic Architecture THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
» Concurrent Round-Robin Dispatching Scheme
» Homogeneous Capacity and Route Assignment
» The Staggering Switch ALL-OPTICAL PACKET SWITCHES
» HYPASS OPTOELECTRONIC PACKET SWITCHES
» STAR-TRACK OPTOELECTRONIC PACKET SWITCHES
» Cisneros and Brackett’s Architecture
» Basic Architecture THE 3M SWITCH
» Cell Delineation Unit THE 3M SWITCH
» VCI-Overwrite Unit Cell Synchronization Unit
» Input and Output Forwarding Engines Input and Output Switch Interfaces
» Route Controller Router Module and Route Controller
» Input Optical Module Output Optical Module Tunable Filters
» Principles of Ping-Pong Arbitration Consider an N-input
» Performance of PPA Implementation of PPA
» Priority PPA Ping-Pong Arbitration Unit
» Component Complexity OIN Complexity
» Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
» Crosstalk Analysis OPTICAL INTERCONNECTION NETWORK FOR
» System Considerations WIRELESS ATM STRUCTURE OVERVIEWS
» NEC’s WATMnet Prototype System
» Olivetti’s Radio ATM LAN Virtual Connection Tree
» BAHAMA Wireless ATM LAN NTT’s Wireless ATM Access
» Radio Physical Layer RADIO ACCESS LAYERS
» Medium Access Control Layer Data Link Control Layer
» Connection Rerouting HANDOFF IN WIRELESS ATM
» Buffering Cell Routing in a COS
» Design of a Mobility-Support Switch
» Performance MOBILITY-SUPPORT ATM SWITCH
» Architectures of Generic Routers
» IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE IP ROUTE LOOKUP BASED ON STANDARD
» Levels 2 and 3 of Data Structure
» Adapting Binary Search for Best-Matching Prefix
» Precomputed 16-Bit Prefix Table Multiway Binary Search: Exploiting the Cache Line
» Lookup Algorithms and Data Structure Construction
» Prefix Update Algorithms IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
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