PERFORMANCE OF TDXP SWITCH

THE TANDEM-CROSSPOINT SWITCH 246

9.2.3 Multicasting Operation

Next, we explain the multicasting mechanism in the TDXP switch. Unicast is a subset of multicast. For multicasting, Steps 1 and 3 are modified a little. The remaining procedures, Steps 2, 4, and 5, are the same as above. The modified procedures, Steps 1 X and 3 X , for multicast are as follows. X Ž . Step 1 A cell at the head of the input buffer sends request signals REQ to all the destination tandem crosspoints according to the routing bits written in the cell header. The routing bits for multicasting are, for example, written using a bit-map scheme. Then go to Step 2. Step 3 X The cell at the head of the input buffer that sent REQ before is sent to all the destination crosspoints on the first switch plane, if no NACK is received from any of the crosspoints polled to the input buffer within a certain time. Then go to Step 4. If even one NACK is received by the input buffer within a certain time, the cell is not sent to any of the destination crosspoints; after the next cell time, go to Step 1 X .

9.3 PERFORMANCE OF TDXP SWITCH

The performance of the TDXP switch was evaluated by event-driven com- puter simulation. The simulation programs were written using the C language. The performance parameters of interest were the maximum throughput, the delay time, and the buffer size required to guarantee a specified cell loss ratio. The maximum throughput is defined as the ratio of the total number of cells transmitted to output ports to the total number of offered input cells. In the estimation of the maximum throughput, all offered input loads are set at 1.0. Assume that cell arrival at N input ports follows a Bernoulli process. When the input traffic load is ␳, an incoming cell arrives with probability ␳ in a cell time, and there is no arrival with probability 1 y ␳. The incoming cells are distributed uniformly to all output ports. The input traffic is assumed to be homogeneous, and it is distributed uniformly to all input ports. Bernoulli traffic is considered. In addition, a simple arbitration mecha- Ž . nism for cell output in the switch round-robin arbitration is established between the crosspoints belonging to the same output port. First we present the performance of the TDXP switch for unicasting traffic. Table 9.1 shows how many tandem switch planes K are needed to obtain the maximum throughput in the TDXP switch architecture. To evalu- ate the maximum throughput, it is assumed that the sizes of the input and output buffers are infinite. We can see that the maximum throughput is almost saturated with K s 2. We thus conclude that K s 2 is large enough to obtain the maximum throughput. Therefore, in the following performance evaluation of the TDXP PERFORMANCE OF TDXP SWITCH 247 TABLE 9.1 Maximum Throughput Determined by the Number K a of Tandem Switch Planes Maximum Throughput K N s 8 N s 16 N s 32 N s 64 N s 128 1 0.618 0.599 0.598 0.588 0.588 2 0.922 0.948 0.970 0.983 0.990 3 0.939 0.962 0.979 0.989 0.994 4 0.942 0.965 0.981 0.990 0.995 a N s switch size. switch, K is set to 2. In addition, we also show the performance of the conventional internal speedup switch with input and output buffers for w x reference. The internal speedup factor L is set to 2 for rough equivalency 9 . The maximum throughput of the TDXP switch increases with switch size N, and is higher than that of the double-speedup switch. Figure 9.5 compares the maximum throughput with those of the internal double-speedup switch Ž . L s 2 and the input buffering switch. The maximum throughput of the TDXP switch decreases with small N, say N F 8, and increases with larger N. The reason is as follows. The probability P that two successive cells at suc Ž . Fig. 9.5 Comparison of maximum throughput. 䊚1997 IEEE. THE TANDEM-CROSSPOINT SWITCH 248 the same input buffer are destined to the same output port is 1rN. When N is small, P is large. As a result, the later cell in the input buffer is likely to suc Ž . be blocked NACK is received because the first cell is still being handled in the tandem crosspoint. On the other hand, if N is large, P is small, i.e., the suc blocking probability is small. The maximum throughput approaches 1.0 with N ™ ⬁, because of P ™ 0. In the double-speedup switch, the maximum suc throughput decreases to a certain value with increasing N, as is true for the input buffering switch. Thus, the maximum throughput of the TDXP switch is higher than that of the double-speedup switch when N is large. The cell transmission delay of the TDXP switch is compared with that of the double-speedup switch with N s 32. The maximum delay, defined as the 99.9 value, and the average delay are shown in Figure 9.6. The maximum and average delay of the TDXP switch are almost the same as those of the Ž . double-speedup switch with small ␳ F 0.85 . However, when the offered load ␳ is larger than 0.85, the maximum and average delay values of the double-speedup switch increase strongly, because the limitation of the maxi- mum throughput is smaller than that of the TDXP switch. In the TDXP switch, although the internal speed is the same as that of the input and output lines and a cell is buffered in a tandem crosspoint before it is Fig. 9.6 Delay performance. PERFORMANCE OF TDXP SWITCH 249 Ž . Fig. 9.7 Delay performance vs. switch size. 䊚1997 IEEE. transmitted to the output ports, the delay performance is better than that of the double-speedup switch. This is simply because the TDXP switch has the higher maximum throughput. The switch size dependence of the cell transmission delay is shown in Figure 9.7. We can see that the maximum and average delay of the TDXP switch do not increase with N, while the delay of the double-speedup switch does. This results from the lower HOL blocking probability of the TDXP switch with large N, as explained in Figure 9.5. Thus, the TDXP switch has scalability in terms of N. Figure 9.8 shows the required buffer sizes per port for an input buffer, an output buffer, and the sum of the input and output buffers, assuming a cell loss ratio below 10 y 9 . As is true for the delay performance results in Figure 9.6, the total size of the TDXP switch is almost the same as that of the double-speedup switch, but with offered loads higher than ␳ s 0.85, that of the double-speedup switch increases very strongly. Therefore, buffer re- sources in the TDXP switch are used effectively. Next, the results of the TDXP switch for multicasting traffic are pre- sented. The multicast cell ratio ␳ is defined as the ratio of offered total mc input cells to offered multicast cells. The distribution of the number of copies is assumed to follow a binomial distribution. THE TANDEM-CROSSPOINT SWITCH 250 Ž . Fig. 9.8 Buffer size requirement. 䊚1997 IEEE. Figures 9.9 and 9.10 show the blocking ratio B for multicasting traffic. block B is defined as the ratio of the offered input cells to the cells not block transmitted from the input buffer on account of HOL blocking. In this case, the offered input traffic load is set to 1.0. The multicast mechanism employed is that presented in Section 9.2.3. The B of the TDXP switch is smaller block than that of the double-speedup switch with N s 32. The reason is as follows. In the double-speedup switch, if at least one of the destination output ports is occupied by another cell belonging to a different input port, the multicast cell is blocked at the HOL in the input buffer. On the other hand, in the TDXP switch, even when the destined output ports are so occupied, the cell is buffered in the tandem crosspoint, and an attempt is made to send it through the next switch plane in the next time slot. Therefore, the following multicast cell in the input buffer can be transmitted to all destination tandem crosspoints as long as none of them is buffering a cell. This benefit of the TDXP switch is large when N is large and the Ž . average number of copies ANC is smallᎏin other words, NrANC is large ᎏ as shown in Figure 9.10. However, if NrANC is small, B of the TDXP block switch is higher than that of the double-speedup switch. For example, we can see such a case with N F 15 and ANC s 4. PERFORMANCE OF TDXP SWITCH 251 Fig. 9.9 Blocking ratio for multicasting. Fig. 9.10 Blocking ratio for multicasting vs. switch size and average number of copies. THE TANDEM-CROSSPOINT SWITCH 252 REFERENCES 1. G. Balboni, M. Collivignarelli, L. Licciardi, A. Paglialunga, G. Rigolio, and F. Zizza, ‘‘From transport backbone to service platform: facing the broadband switch evolution,’’ Proc. ISS ’95, pp. 26, 1995. 2. T. Chaney, J. A. Fingerhut, M. Flucke, and J. S. Turner, ‘‘Design of a gigabit ATM switch,’’ Proc. IEEE INFOCOM ’97, pp. 2᎐11, 1997. 3. M. Collivignarelli, A. Daniele, P. De Nicola, L. Licciardi, M. Turolla, and A. Zappalorto, ‘‘A complete set of VLSI circuits for ATM switching,’’ Proc. IEEE GLOBECOM ’94, pp.134᎐138, 1994. 4. K. Genda, Y. Doi, K. Endo, T. Kawamura, and S. Sasaki, ‘‘A 160-Gbrs ATM switching system using an internal speed-up crossbar switch,’’ Proc. IEEE GLOBECOM ’94, pp. 123᎐133, 1994. 5. M. J. Karol, M. G. Hluchyj, and S. P. Morgan, ‘‘Input versus output queueing on a space-division packet switch,’’ IEEE Trans. Commun., vol. COM-35, pp. 1347᎐1356, Dec. 1987. 6. T. Kawamura, H. Ichino, M. Suzuki, K. Genda, and Y. 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Yamanaka, ‘‘A high-speed tandem-crosspoint ATM switch archi- tecture with input and output buffers,’’ IEICE Trans. Commun., vol. E81-B, no. 2, pp. 215᎐223, 1998. 13. J. S. Turner, ‘‘Design of a broadcast packet switching networks,’’ IEEE Trans. Commun., vol. 36, pp. 734᎐743, 1988. 14. N. Yamanaka, K. Endo, K. Genda, H. Fukuda, T. Kishimoto, and S. Sasaki, ‘‘320 Gbrs high-speed ATM switching system hardware technologies based on copper- polyimide MCM,’’ IEEE Trans. CPMT, 1996, vol.18, pp. 83᎐91, 1995. H. Jonathan Chao, Cheuk H. Lam, Eiji Oki Copyright 䊚 2001 John Wiley Sons, Inc. Ž . Ž . ISBNs: 0-471-00454-5 Hardback ; 0-471-22440-5 Electronic CHAPTER 10 CLOS-NETWORK SWITCHES In Chapter 6 and Chapter 7, we have studied how to recursively construct a large switch from smaller switch modules based on the channel grouping principle. In such a construction, every input is broadcast to each first-stage module, and the input size of first-stage modules is still the same as that of the entire switch. In this chapter we consider a different approach to build modular switches. Ž . The architecture is based on the Clos network see Fig. 10.1 . Switch modules are arranged in three stages, and every module is interconnected with every module in the adjacent stage via a unique link. In this book, the three stages are referred as input stage, middle stage, and output stage, respectively. The modules in those stages are accordingly called input modules, central mod- ules, and output modules. Each module is assumed to be nonblocking and could be, for example, one of the crossbar switches described previously. Inputs are partitioned into groups, and only one group of inputs are con- nected to each input module, thereby reducing the size of each module. One may wonder why we are not just considering a two-stage interconnec- tion network in which every pair of modules of adjacent stages are intercon- nected with a dedicated link. In that case, no two cells can be simultaneously transmitted between any pair of modules, because there is just one path between them. In a Clos network, however, two cells from an input module can take distinct paths via different central modules to get to the same Ž . module at the output stage see Fig. 10.2 . The central modules in the middle stage can be looked on as routing resources shared by all input and output modules. One can expect that this will give a better tradeoff between the switch performance and the complexity. 253 CLOS-NETWORK SWITCHES 254 Fig. 10.1 A growable switch configuration. Fig. 10.2 Routing in a Clos network. ROUTING PROPERTIES AND SCHEDULING METHODS