Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING

THE ABACUS SWITCH 220 TABLE 7.5 Complexity Comparison of Three Approaches for a 160-Gbitr r r r rs Abacus Switch MMCN BMCN Resequencing 2 2 2 2 No. of switch elements LN q L Nn N q Nn LN No. of interstage links JLN JN No. of internal buffers JK No. of MP bits K K K N q LM y 1 N Out-of-sequence delay = 424 LM Routing delay in bits n q Ln y 1 n q LM y 1 N q LM y 1 Switch size N 1024 1024 1024 Group size M 16 16 16 Output exp. ratio L 1.25 1.25 1.25 Module size n 128 128 128 No. of switch elements 1,515,520 1,179,648 1,310,720 No. of interstage links 10,240 8,192 No. of internal buffers 512 No. of MP bits 64 64 64 Out-of-sequence delay 156 Routing delay in bits 287 147 1,043 port. For a switch capacity of 160 Gbitrs, the delay caused by resequencing cells is at least 156 cell slot times.

7.7 ABACUS SWITCH FOR PACKET SWITCHING

The abacus switch can also handle variable-length packets. To preserve the cell 1 sequence in a packet, two cell scheduling schemes are used at the input buffers. The packet interlea®ing scheme transfers all cells in a packet consecu- tively, while the cell interlea®ing scheme transfers cells from different inputs and reassembles them at the output.

7.7.1 Packet Interleaving

A packet switch using the packet interleaving technique is shown in Figure 7.24. The switch consists of a memoryless nonblocking multicast grouping Ž . Ž . network MGN , input port controllers IPCs , and output port controllers Ž . OPCs . Arriving cells are stored in an input buffer until the last cell of the packet arrives. When the last cell arrives, the packet is then eligible for Ž . transmission to output port s . In the packet interleaving scheme, all cells belonging to the same packet are transferred consecutively. That is, if the first cell in the packet wins the 1 The cell discussed in this section is just a fixed-length segment of a packet and does not have to be 53 bytes like an ATM cell. ABACUS SWITCH FOR PACKET SWITCHING 221 Fig. 7.24 A packet switch with packet interleaving. output port contention for a destination among the contending input ports, all the following cells of the packet will be transferred consecutively to the destination. A packet interleaving switch can be easily implemented by the abacus switch. Only the first cells of HOL packets can contend for output ports. The contention among the first cells of HOL packets can be resolved by properly assigning priority fields to them. The priority field of a cell has 1 q log N 2 bits. Among them, the log N-bit field is used to achieve fair contention by 2 dynamically changing its value as in the abacus switch. Prior to the con- Ž . tention resolution, the most significant bit MSB of the priority field is set to Ž . 1 low priority . As soon as the first cell of an HOL packet wins the Ž . contention known from the feedback priorities , the MSB of the priority Ž field of all the following cells in the same packet is asserted to 0 high . priority . As soon as the last cell of the packet is successfully sent to the output, the MSB is set to 1 for the next packet. As a result, it is ensured that cells belonging to the same packet are transferred consecutively. Figure 7.25 shows the average packet delay vs. offered load for a packet switch with packet interleaving. In the simulations, it is assumed that the traffic source is an on᎐off model. The packet size is assumed to have a truncated geometric distribution with an average packet size of 10 cells and Ž maximum packet size of 32 cells to accommodate the maximum Ethernet . frame size . The packet delay through the switch is defined as follows. When the last cell of a packet arrives at an input buffer, the packet is timestamped THE ABACUS SWITCH 222 Fig. 7.25 Delay performance of a packet switch with packet interleaving. with an arrival time. When the last cell of a packet leaves the output buffer, the packet is timestamped with a departure time. The difference between the arrival time and the departure time is defined as the packet delay. When Ž . there is no internal speedup S s 1 in the switch fabric, the delay perfor- mance of the packet interleaving switch is very poor, mainly due to the HOL blocking. The delay᎐throughput performance is improved by increasing the Ž . speedup factor S e.g., S s 2 . Note that the input buffer’s average delay is much smaller than the output buffer’s average delay. With an internal speedup of two, the output buffer’s average delay dominates the total average delay and is very close to that of the output-buffered switch.

7.7.2 Cell Interleaving