Performance of SDA Switch
8.2.2 Performance of SDA Switch
SDA switch performance was evaluated in terms of delay time and crosspoint buffer size by computer simulation. It is assumed that, in an N = N cross- point-buffered switch, the input traffic is random, the input load is 0.95, and cells are distributed uniformly to all crosspoint buffers belonging to the same input line. The SDA switch ensures delay time fairness. Figure 8.3 shows the proba- bility of the delay time being larger than d at N s 8. The probability is shown for each crosspoint buffer entered by cells. The delay time is defined as the time from the cell’s entering the crosspoint buffer until it reaches the Ž . Fig. 8.3 Delay performance of SDA switch. 䊚1997 IEEE. CROSSPOINT BUFFERED SWITCHES 232 Ž . Fig. 8.4 Maximum delay time. 䊚1997 IEEE. output line. In the SDA switch, when d is more than about 10 cell times, all delay times have basically the same probability and delay time fairness is Ž achieved. Since it takes at least N s 8 cell times for the cell in the top crosspoint buffer to enter the output line, fairness is not maintained at . smaller values. In addition, when d is larger than a certain time, the probability of the SDA switch delay time being larger than d is smaller than that of the RR switch, as shown in Figure 8.3. This is because, in the SDA switch, the cell with the largest delay time is selected. This effect becomes clearer as N increases. Figure 8.4 shows that the Ž y 4 . maximum delay time 10 quantile of the SDA does not change very much when N increases, while that of the RR switch increases rapidly. Further- 7 Ž . more, maximum SDA delay is smaller than 2 s 128 cell times even at large N. This means that synchronous counter size is just S s 8, as men- tioned before. The required crosspoint buffer size of the SDA switch is smaller than that of the switch, as shown in Figure 8.5. The required buffer sizes were estimated so as to guarantee the cell loss ratio of 10 y 9 . In the SDA switch, since the required buffer sizes differ for the crosspoint buffers, Figure 8.5 Ž . Ž shows the smallest top crosspoint buffer and the largest bottom crosspoint . buffer sizes. The sizes of the intermediate crosspoint buffers lie between these two values. Because the SDA switch has shorter delay time as ex- plained before, the queue length of the crosspoint buffer is also reduced. This is why the crosspoint buffer size of the SDA switch is less than that of the RR switch. The switch throughput of the SDA switch increases as the switch size N increases, as shown in Figure 8.6. Since the arbitration time does not limit SCALABLE DISTRIBUTED-ARBITRATION SWITCH 233 Ž . Fig. 8.5 Required buffer size. 䊚1997 IEEE. the output-line speed, the SDA switch can be expanded to achieve high switch throughput even if N is large. The switch throughput is calculated as C N, where C is the maximum output line speed. max max On the other hand, the switch throughput of the RR-based switch does not increase when N becomes large. Instead it depends on the transmission delay of the control signal in a crosspoint. The RR arbitration time limits the output line speed. The RR-based switch is not expandable, because of the limitation of the RR arbitration time. Ž . Fig. 8.6 Switch throughput vs. switch size. 䊚1997 IEEE. CROSSPOINT BUFFERED SWITCHES 2348.3 MULTIPLE-QOS SDA SWITCH
Parts
» ATM Switch Structure ATM SWITCH SYSTEMS
» DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
» Internal Link Blocking Output Port Contention Head-of-Line Blocking
» Shared-Medium Switch Time-Division Switching
» Single-Path Switches Space-Division Switching
» Multiple-Path Switches Space-Division Switching
» Internally Buffered Switches Recirculation Buffered Switches
» Input- and Output-Buffered Switches Virtual-Output-Queueing Switches
» Input-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Completely Shared-Buffer Switches PERFORMANCE OF BASIC SWITCHES
» Bernoulli Arrival Process and Random Traffic On–Off Model and Bursty Traffic
» Multiline Input Smoothing Speedup Parallel Switch
» Window-Based Lookahead Selection Increasing Scheduling Efficiency
» VOQ-Based Matching Increasing Scheduling Efficiency
» Parallel Iterative Matching PIM Iterative Round-Robin Matching iRRM
» Iterative Round-Robin with SLIP i SLIP
» Dual Round-Robin Matching DRRM
» Round-Robin Greedy Scheduling SCHEDULING ALGORITHMS
» Bidirectional Arbiter Design of Round-Robin Arbiters r
» Token Tunneling This section introduces a more efficient arbi-
» Most-Urgent-Cell-First Algorithm MUCFA OUTPUT-QUEUING EMULATION
» Critical Cell First CCF Last In, Highest Priority LIHP
» LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST JONATHAN CHAO CHEUK LAM
» LINKED LIST APPROACH JONATHAN CHAO CHEUK LAM
» CONTENT-ADDRESSABLE MEMORY APPROACH JONATHAN CHAO CHEUK LAM
» Washington University Gigabit Switch
» Shared-Memory Switch with a Multicast Logical Queue Shared-Memory Switch with Cell Copy
» Shared-Memory Switch with Address Copy
» BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
» Three-Phase Implementation Ring Reservation
» BATCHER-SORTING NETWORK THE SUNSHINE SWITCH
» Tandem Banyan Switch DEFLECTION ROUTING
» Shuffle-Exchange Network with Deflection Routing
» Dual Shuffle-Exchange Network with Error-Correcting Routing
» Generalized Self-Routing Algorithm Broadcast Banyan Network
» Boolean Interval Splitting Algorithm Nonblocking Condition of Broadcast Banyan Networks A
» Encoding Process MULTICAST COPY NETWORKS
» Concentration Decoding Process Overflow and Call Splitting
» A. Cyclic Running Adder Network Figure 5.34 shows the struc-
» Concentration The starting point in a CRAN may not be port 0,
» Basic Architecture SINGLE-STAGE KNOCKOUT SWITCH
» Knockout Concentration Principle SINGLE-STAGE KNOCKOUT SWITCH
» Construction of the Concentrator
» Maximum Throughput CHANNEL GROUPING PRINCIPLE
» Two-Stage Configuration A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Multicast Grouping Network A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Translation Tables A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Cross-Stuck CS Fault Toggle-Stuck TS Fault Verticalr
» Toggle-Stuck and Cross-Stuck Cases
» Vertical-Stuck and Horizontal-Stuck Cases
» Cross-Stuck and Toggle-Stuck Cases
» Vertical-Stuck Case Horizontal-Stuck SWE Case
» APPENDIX JONATHAN CHAO CHEUK LAM
» BASIC ARCHITECTURE JONATHAN CHAO CHEUK LAM
» MULTICAST CONTENTION RESOLUTION ALGORITHM
» IMPLEMENTATION OF INPUT PORT CONTROLLER
» Cell Loss Probability PERFORMANCE
» ATM ROUTING AND CONCENTRATION CHIP
» Memoryless Multistage Concentration Network
» Buffered Multistage Concentration Network
» Resequencing Cells ENHANCED ABACUS SWITCH
» Complexity Comparison ENHANCED ABACUS SWITCH
» Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» Cell Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» MSDA Structure MULTIPLE-QOS SDA SWITCH
» OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES OVERVIEW OF INPUT
» Basic Architecture Unicasting Operation
» ROUTING PROPERTIES AND SCHEDULING METHODS
» A SUBOPTIMAL STRAIGHT MATCHING METHOD
» Basic Architecture Distributed and Random Arbitration
» Basic Architecture THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
» Concurrent Round-Robin Dispatching Scheme
» Homogeneous Capacity and Route Assignment
» The Staggering Switch ALL-OPTICAL PACKET SWITCHES
» HYPASS OPTOELECTRONIC PACKET SWITCHES
» STAR-TRACK OPTOELECTRONIC PACKET SWITCHES
» Cisneros and Brackett’s Architecture
» Basic Architecture THE 3M SWITCH
» Cell Delineation Unit THE 3M SWITCH
» VCI-Overwrite Unit Cell Synchronization Unit
» Input and Output Forwarding Engines Input and Output Switch Interfaces
» Route Controller Router Module and Route Controller
» Input Optical Module Output Optical Module Tunable Filters
» Principles of Ping-Pong Arbitration Consider an N-input
» Performance of PPA Implementation of PPA
» Priority PPA Ping-Pong Arbitration Unit
» Component Complexity OIN Complexity
» Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
» Crosstalk Analysis OPTICAL INTERCONNECTION NETWORK FOR
» System Considerations WIRELESS ATM STRUCTURE OVERVIEWS
» NEC’s WATMnet Prototype System
» Olivetti’s Radio ATM LAN Virtual Connection Tree
» BAHAMA Wireless ATM LAN NTT’s Wireless ATM Access
» Radio Physical Layer RADIO ACCESS LAYERS
» Medium Access Control Layer Data Link Control Layer
» Connection Rerouting HANDOFF IN WIRELESS ATM
» Buffering Cell Routing in a COS
» Design of a Mobility-Support Switch
» Performance MOBILITY-SUPPORT ATM SWITCH
» Architectures of Generic Routers
» IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE IP ROUTE LOOKUP BASED ON STANDARD
» Levels 2 and 3 of Data Structure
» Adapting Binary Search for Best-Matching Prefix
» Precomputed 16-Bit Prefix Table Multiway Binary Search: Exploiting the Cache Line
» Lookup Algorithms and Data Structure Construction
» Prefix Update Algorithms IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
Show more