Homogeneous Capacity and Route Assignment
10.5.1 Homogeneous Capacity and Route Assignment
For uniform traffic, where the distribution of traffic loading between input modules and output modules is homogeneous, the fm edges of each node can be evenly divided into k groups, where k is the total number of input or output modules. Each group contains g s fmrk edges between any input᎐output pair, where the frame size f should be chosen to make the group size g an integer. The edges of this capacity graph can be easily colored by the Latin square given in Table 10.1, where each A , 0 F i F k y 1, i represents a set of distinct colors, e.g., 4 4 A s 0, 1, . . . , g y 1 , A s g , g q 1, . . . , 2 g y 1 , . . . 1 A s k y 1 g , k y 1 g q 1, . . . , kg y 1 4 Ž . Ž . ky1 4 Since each number in the set 0, 1, . . . , fm y 1 appears only once in any row or column in the table, it is a legitimate edge coloring of the capacity graph. Ž . The assignment a s t, r of an edge between the I ᎐O pair indicates that i j the central module r will connect input module i to output module j in the t th slot of every frame. As an example, for m s 3 and k s 2, we can choose 4 f s 2 and thus g s 3. Then, the groups of colors are A s 0, 1, 2 and 4 A s 3, 4, 5 , respectively. The procedure described above is illustrated in 1 Table 10.2, and the correspondence between the route assignments and the connection patterns in the middle stage is shown in Figure 10.13. Ž . In the above example, since the number of central modules m is greater Ž . than the number of input modules k , it is possible that more than one central module is assigned to some input᎐output pair in one time slot. In the case that m - k, there are not enough central modules for all input᎐output TABLE 10.1 Latin Square Assignment O O O ⭈⭈⭈ O 1 2 ky1 I A A A ⭈⭈⭈ A 1 2 ky1 I A A A ⭈⭈⭈ A 1 ky1 1 ky2 . . . . . . . . . . . . . . . I A A A ⭈⭈⭈ A ky1 1 2 3 THE PATH SWITCH 273 TABLE 10.2 Route Assignment by Latin Square for Uniform Traffic Color Color O O a s rf q t 1 2 3 4 5 1 Central module ? I 0, 1, 2 3, 4, 5 q r s arf 1 1 2 2 Time slot I 3, 4, 5 0, 1, 2 y s a mod f 1 1 1 1 Latin square: edge coloring Transformation from color assignment into time᎐space pair y Central-module assignment Central Central Module O O Module O O 1 1 I 0, 1 2 I 1, 2 I 2 0, 1 I 1, 2 1 1 Time slot 0 Time slot 1 Ž . Fig. 10.13 Route scheduling in the middle stage for uniform traffic. 䊚1997 IEEE. CLOS-NETWORK SWITCHES 274 Fig. 10.14 Route scheduling in central modules for the second example of uniform Ž . traffic. 䊚1997 IEEE. pairs in one time slot assignment. Nevertheless, the total number of central modules assigned to every input᎐output pair within a frame should be the same for uniform input traffic to fulfill the capacity requirement, and that number is equal to g s fmrk. This point is illustrated in the following example. For m s 4 and k s 6, we choose f s 3 and g s 2. The same method will result in the connection patterns shown in Figure 10.14. It is easy Ž . to verify that the number of central modules paths, edges assigned for each input᎐output pair is equal to g s 2 per f s 3 slots.10.5.2 Heterogeneous Capacity Assignment
Parts
» ATM Switch Structure ATM SWITCH SYSTEMS
» DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
» Internal Link Blocking Output Port Contention Head-of-Line Blocking
» Shared-Medium Switch Time-Division Switching
» Single-Path Switches Space-Division Switching
» Multiple-Path Switches Space-Division Switching
» Internally Buffered Switches Recirculation Buffered Switches
» Input- and Output-Buffered Switches Virtual-Output-Queueing Switches
» Input-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Completely Shared-Buffer Switches PERFORMANCE OF BASIC SWITCHES
» Bernoulli Arrival Process and Random Traffic On–Off Model and Bursty Traffic
» Multiline Input Smoothing Speedup Parallel Switch
» Window-Based Lookahead Selection Increasing Scheduling Efficiency
» VOQ-Based Matching Increasing Scheduling Efficiency
» Parallel Iterative Matching PIM Iterative Round-Robin Matching iRRM
» Iterative Round-Robin with SLIP i SLIP
» Dual Round-Robin Matching DRRM
» Round-Robin Greedy Scheduling SCHEDULING ALGORITHMS
» Bidirectional Arbiter Design of Round-Robin Arbiters r
» Token Tunneling This section introduces a more efficient arbi-
» Most-Urgent-Cell-First Algorithm MUCFA OUTPUT-QUEUING EMULATION
» Critical Cell First CCF Last In, Highest Priority LIHP
» LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST JONATHAN CHAO CHEUK LAM
» LINKED LIST APPROACH JONATHAN CHAO CHEUK LAM
» CONTENT-ADDRESSABLE MEMORY APPROACH JONATHAN CHAO CHEUK LAM
» Washington University Gigabit Switch
» Shared-Memory Switch with a Multicast Logical Queue Shared-Memory Switch with Cell Copy
» Shared-Memory Switch with Address Copy
» BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
» Three-Phase Implementation Ring Reservation
» BATCHER-SORTING NETWORK THE SUNSHINE SWITCH
» Tandem Banyan Switch DEFLECTION ROUTING
» Shuffle-Exchange Network with Deflection Routing
» Dual Shuffle-Exchange Network with Error-Correcting Routing
» Generalized Self-Routing Algorithm Broadcast Banyan Network
» Boolean Interval Splitting Algorithm Nonblocking Condition of Broadcast Banyan Networks A
» Encoding Process MULTICAST COPY NETWORKS
» Concentration Decoding Process Overflow and Call Splitting
» A. Cyclic Running Adder Network Figure 5.34 shows the struc-
» Concentration The starting point in a CRAN may not be port 0,
» Basic Architecture SINGLE-STAGE KNOCKOUT SWITCH
» Knockout Concentration Principle SINGLE-STAGE KNOCKOUT SWITCH
» Construction of the Concentrator
» Maximum Throughput CHANNEL GROUPING PRINCIPLE
» Two-Stage Configuration A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Multicast Grouping Network A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Translation Tables A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Cross-Stuck CS Fault Toggle-Stuck TS Fault Verticalr
» Toggle-Stuck and Cross-Stuck Cases
» Vertical-Stuck and Horizontal-Stuck Cases
» Cross-Stuck and Toggle-Stuck Cases
» Vertical-Stuck Case Horizontal-Stuck SWE Case
» APPENDIX JONATHAN CHAO CHEUK LAM
» BASIC ARCHITECTURE JONATHAN CHAO CHEUK LAM
» MULTICAST CONTENTION RESOLUTION ALGORITHM
» IMPLEMENTATION OF INPUT PORT CONTROLLER
» Cell Loss Probability PERFORMANCE
» ATM ROUTING AND CONCENTRATION CHIP
» Memoryless Multistage Concentration Network
» Buffered Multistage Concentration Network
» Resequencing Cells ENHANCED ABACUS SWITCH
» Complexity Comparison ENHANCED ABACUS SWITCH
» Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» Cell Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» MSDA Structure MULTIPLE-QOS SDA SWITCH
» OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES OVERVIEW OF INPUT
» Basic Architecture Unicasting Operation
» ROUTING PROPERTIES AND SCHEDULING METHODS
» A SUBOPTIMAL STRAIGHT MATCHING METHOD
» Basic Architecture Distributed and Random Arbitration
» Basic Architecture THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
» Concurrent Round-Robin Dispatching Scheme
» Homogeneous Capacity and Route Assignment
» The Staggering Switch ALL-OPTICAL PACKET SWITCHES
» HYPASS OPTOELECTRONIC PACKET SWITCHES
» STAR-TRACK OPTOELECTRONIC PACKET SWITCHES
» Cisneros and Brackett’s Architecture
» Basic Architecture THE 3M SWITCH
» Cell Delineation Unit THE 3M SWITCH
» VCI-Overwrite Unit Cell Synchronization Unit
» Input and Output Forwarding Engines Input and Output Switch Interfaces
» Route Controller Router Module and Route Controller
» Input Optical Module Output Optical Module Tunable Filters
» Principles of Ping-Pong Arbitration Consider an N-input
» Performance of PPA Implementation of PPA
» Priority PPA Ping-Pong Arbitration Unit
» Component Complexity OIN Complexity
» Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
» Crosstalk Analysis OPTICAL INTERCONNECTION NETWORK FOR
» System Considerations WIRELESS ATM STRUCTURE OVERVIEWS
» NEC’s WATMnet Prototype System
» Olivetti’s Radio ATM LAN Virtual Connection Tree
» BAHAMA Wireless ATM LAN NTT’s Wireless ATM Access
» Radio Physical Layer RADIO ACCESS LAYERS
» Medium Access Control Layer Data Link Control Layer
» Connection Rerouting HANDOFF IN WIRELESS ATM
» Buffering Cell Routing in a COS
» Design of a Mobility-Support Switch
» Performance MOBILITY-SUPPORT ATM SWITCH
» Architectures of Generic Routers
» IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE IP ROUTE LOOKUP BASED ON STANDARD
» Levels 2 and 3 of Data Structure
» Adapting Binary Search for Best-Matching Prefix
» Precomputed 16-Bit Prefix Table Multiway Binary Search: Exploiting the Cache Line
» Lookup Algorithms and Data Structure Construction
» Prefix Update Algorithms IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
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