Homogeneous Capacity and Route Assignment

CLOS-NETWORK SWITCHES 272 assigned to a route from I to O in the t th time slot of every cycle. Adopting i j the convention in TDMA system, each cycle will be called a frame, and the period f the frame size. As illustrated by the example shown in Figure 10.12, where m s 3 and f s 2, the decomposition of the edge coloring into assign- ment pairs guarantees that route assignments are either space-interleaved or Ž . time-interleaved. Thus, the relation 10.7 will be called the time᎐space interlea®ing principle.

10.5.1 Homogeneous Capacity and Route Assignment

For uniform traffic, where the distribution of traffic loading between input modules and output modules is homogeneous, the fm edges of each node can be evenly divided into k groups, where k is the total number of input or output modules. Each group contains g s fmrk edges between any input᎐output pair, where the frame size f should be chosen to make the group size g an integer. The edges of this capacity graph can be easily colored by the Latin square given in Table 10.1, where each A , 0 F i F k y 1, i represents a set of distinct colors, e.g., 4 4 A s 0, 1, . . . , g y 1 , A s g , g q 1, . . . , 2 g y 1 , . . . 1 A s k y 1 g , k y 1 g q 1, . . . , kg y 1 4 Ž . Ž . ky1 4 Since each number in the set 0, 1, . . . , fm y 1 appears only once in any row or column in the table, it is a legitimate edge coloring of the capacity graph. Ž . The assignment a s t, r of an edge between the I ᎐O pair indicates that i j the central module r will connect input module i to output module j in the t th slot of every frame. As an example, for m s 3 and k s 2, we can choose 4 f s 2 and thus g s 3. Then, the groups of colors are A s 0, 1, 2 and 4 A s 3, 4, 5 , respectively. The procedure described above is illustrated in 1 Table 10.2, and the correspondence between the route assignments and the connection patterns in the middle stage is shown in Figure 10.13. Ž . In the above example, since the number of central modules m is greater Ž . than the number of input modules k , it is possible that more than one central module is assigned to some input᎐output pair in one time slot. In the case that m - k, there are not enough central modules for all input᎐output TABLE 10.1 Latin Square Assignment O O O ⭈⭈⭈ O 1 2 ky1 I A A A ⭈⭈⭈ A 1 2 ky1 I A A A ⭈⭈⭈ A 1 ky1 1 ky2 . . . . . . . . . . . . . . . I A A A ⭈⭈⭈ A ky1 1 2 3 THE PATH SWITCH 273 TABLE 10.2 Route Assignment by Latin Square for Uniform Traffic Color Color O O a s rf q t 1 2 3 4 5 1 Central module ? I 0, 1, 2 3, 4, 5 q r s arf 1 1 2 2 Time slot I 3, 4, 5 0, 1, 2 y s a mod f 1 1 1 1 Latin square: edge coloring Transformation from color assignment into time᎐space pair y Central-module assignment Central Central Module O O Module O O 1 1 I 0, 1 2 I 1, 2 I 2 0, 1 I 1, 2 1 1 Time slot 0 Time slot 1 Ž . Fig. 10.13 Route scheduling in the middle stage for uniform traffic. 䊚1997 IEEE. CLOS-NETWORK SWITCHES 274 Fig. 10.14 Route scheduling in central modules for the second example of uniform Ž . traffic. 䊚1997 IEEE. pairs in one time slot assignment. Nevertheless, the total number of central modules assigned to every input᎐output pair within a frame should be the same for uniform input traffic to fulfill the capacity requirement, and that number is equal to g s fmrk. This point is illustrated in the following example. For m s 4 and k s 6, we choose f s 3 and g s 2. The same method will result in the connection patterns shown in Figure 10.14. It is easy Ž . to verify that the number of central modules paths, edges assigned for each input᎐output pair is equal to g s 2 per f s 3 slots.

10.5.2 Heterogeneous Capacity Assignment