Speedup Data Packet Flow
11.4.2 A Terabit IP Router Architecture
w x Figure 11.20 depicts four major elements in the terabit IP router 24 : the OIN supporting nonblocking and high-capacity switching, the Ping-Pong Ž . arbitration unit PAU resolving the output contention and controlling the switching devices, the RMs performing IP packet forwarding, and the RC constructing routing information for the RMs. There are two kinds of RM: Ž . Ž . input RM IRM and output RM ORM . Both the IRMs and the ORMs Ž . implement IP packet buffering, route table lookup, packet filtering, and versatile interfaces, such as OC-3, OC12, OC-48, and Gigabit Ethernet. The interconnection between the RC and the RMs can be implemented with dedicated buses or through the OIN. Figure 11.20 simply illustrates the bus-based approach.11.4.2.1 Speedup
The fixed-length segment switching technique is com- monly adopted in high-capacity IP routers to achieve high-speed switching and better system performance. Ž . Figure 11.21 a suggests that a speedup factor of two is required to achieve nearly 100 throughput under bursty traffic with geometric distribution and Ž . an average burst size of 10 packet segments. Figure 11.21 b shows the corresponding average delay. The total average delay of input and output queuing is very close to the theoretical bound of purely output queuing. The input delay is an order smaller than the total delay, hinting that an input- OPTICAL PACKET SWITCHES 304 Ž . Ž . Fig. 11.21 Switch performance: a throughput, b average delay. queued switch with speedup 2, on average, will perform as nearly well as a purely output-queued switch. Ž . The speedup induces more challenges in two aspects: 1 doubling the Ž . switch transmission speed to 10 Gbitrs, and 2 halving the arbitration time constraint. The first challenge can be easily met with optical interconnection technology, while the second can be met by the PPA scheme described in Section 11.4.5. OPTICAL INTERCONNECTION NETWORK FOR TERABIT IP ROUTERS 305 Fig. 11.22 The flow of packets across the router.11.4.2.2 Data Packet Flow
A data segment unit of 64 bytes is chosen to Ž . accommodate the shortest IP packets 40 bytes . Variable-length IP packets are segmented before being passed through the switch. Figure 11.22 depicts Ž . the flow of packets across the router. A simple round-robin RR packet Ž . scheduler is used at each input line interface ILI to arrange the packet Ž . arrivals from different interfaces see also Fig. 11.20 . It uses a FIFO buffer per interface to store incoming packets. Since the output line speed of the scheduler depends on all interfaces, it can be shown that the maximum packet backlog at each input line FIFO is just twice the maximum IP packet size, so the same large buffer can be chosen to avoid any packet loss. Ž . The output packets of the scheduler enter the input switch interface ISI in which packet segmentation takes place. While a packet is being seg- Ž . mented, its IP header is first checked by the input packet filter IPF for Ž . network security and flow classification i.e., inbound filtering , as shown in Figure 11.20. Afterwards, the header is sent to the input forwarding engine Ž . Ž . IFE for IP table lookup, deciding which ORM s this packet is destined for. Data segments are stored in a FIFO while waiting for arbitration before being forwarded through the OIN. The forwarding sequence is packet by packet, not cell by cell, for each ISI, in order to simplify the reassembly. The input port number is added to each segment before it enters the OIN for ensuring correct packet reassembly at output ports. Segments of a packet arriving at an output port may be interleaved with those from other input ports. While a packet is being reassembled, its IP OPTICAL PACKET SWITCHES 306 Ž . header can be sent to the output packet filter OPF for outbound filtering Ž . and then to the output forwarding engine OFE for another IP route lookup Ž . to decide which outgoing interface s this packet should be destined for. The Ž . packets are then broadcast at the output line interface OLI to all desirable interfaces. Each interface can maintain two FIFOs supporting two traffic Ž . Ž . priorities: real-time RT and non-real-time NRT packets.11.4.3 Router Module and Route Controller
Parts
» ATM Switch Structure ATM SWITCH SYSTEMS
» DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
» Internal Link Blocking Output Port Contention Head-of-Line Blocking
» Shared-Medium Switch Time-Division Switching
» Single-Path Switches Space-Division Switching
» Multiple-Path Switches Space-Division Switching
» Internally Buffered Switches Recirculation Buffered Switches
» Input- and Output-Buffered Switches Virtual-Output-Queueing Switches
» Input-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Completely Shared-Buffer Switches PERFORMANCE OF BASIC SWITCHES
» Bernoulli Arrival Process and Random Traffic On–Off Model and Bursty Traffic
» Multiline Input Smoothing Speedup Parallel Switch
» Window-Based Lookahead Selection Increasing Scheduling Efficiency
» VOQ-Based Matching Increasing Scheduling Efficiency
» Parallel Iterative Matching PIM Iterative Round-Robin Matching iRRM
» Iterative Round-Robin with SLIP i SLIP
» Dual Round-Robin Matching DRRM
» Round-Robin Greedy Scheduling SCHEDULING ALGORITHMS
» Bidirectional Arbiter Design of Round-Robin Arbiters r
» Token Tunneling This section introduces a more efficient arbi-
» Most-Urgent-Cell-First Algorithm MUCFA OUTPUT-QUEUING EMULATION
» Critical Cell First CCF Last In, Highest Priority LIHP
» LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST JONATHAN CHAO CHEUK LAM
» LINKED LIST APPROACH JONATHAN CHAO CHEUK LAM
» CONTENT-ADDRESSABLE MEMORY APPROACH JONATHAN CHAO CHEUK LAM
» Washington University Gigabit Switch
» Shared-Memory Switch with a Multicast Logical Queue Shared-Memory Switch with Cell Copy
» Shared-Memory Switch with Address Copy
» BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
» Three-Phase Implementation Ring Reservation
» BATCHER-SORTING NETWORK THE SUNSHINE SWITCH
» Tandem Banyan Switch DEFLECTION ROUTING
» Shuffle-Exchange Network with Deflection Routing
» Dual Shuffle-Exchange Network with Error-Correcting Routing
» Generalized Self-Routing Algorithm Broadcast Banyan Network
» Boolean Interval Splitting Algorithm Nonblocking Condition of Broadcast Banyan Networks A
» Encoding Process MULTICAST COPY NETWORKS
» Concentration Decoding Process Overflow and Call Splitting
» A. Cyclic Running Adder Network Figure 5.34 shows the struc-
» Concentration The starting point in a CRAN may not be port 0,
» Basic Architecture SINGLE-STAGE KNOCKOUT SWITCH
» Knockout Concentration Principle SINGLE-STAGE KNOCKOUT SWITCH
» Construction of the Concentrator
» Maximum Throughput CHANNEL GROUPING PRINCIPLE
» Two-Stage Configuration A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Multicast Grouping Network A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Translation Tables A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Cross-Stuck CS Fault Toggle-Stuck TS Fault Verticalr
» Toggle-Stuck and Cross-Stuck Cases
» Vertical-Stuck and Horizontal-Stuck Cases
» Cross-Stuck and Toggle-Stuck Cases
» Vertical-Stuck Case Horizontal-Stuck SWE Case
» APPENDIX JONATHAN CHAO CHEUK LAM
» BASIC ARCHITECTURE JONATHAN CHAO CHEUK LAM
» MULTICAST CONTENTION RESOLUTION ALGORITHM
» IMPLEMENTATION OF INPUT PORT CONTROLLER
» Cell Loss Probability PERFORMANCE
» ATM ROUTING AND CONCENTRATION CHIP
» Memoryless Multistage Concentration Network
» Buffered Multistage Concentration Network
» Resequencing Cells ENHANCED ABACUS SWITCH
» Complexity Comparison ENHANCED ABACUS SWITCH
» Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» Cell Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» MSDA Structure MULTIPLE-QOS SDA SWITCH
» OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES OVERVIEW OF INPUT
» Basic Architecture Unicasting Operation
» ROUTING PROPERTIES AND SCHEDULING METHODS
» A SUBOPTIMAL STRAIGHT MATCHING METHOD
» Basic Architecture Distributed and Random Arbitration
» Basic Architecture THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
» Concurrent Round-Robin Dispatching Scheme
» Homogeneous Capacity and Route Assignment
» The Staggering Switch ALL-OPTICAL PACKET SWITCHES
» HYPASS OPTOELECTRONIC PACKET SWITCHES
» STAR-TRACK OPTOELECTRONIC PACKET SWITCHES
» Cisneros and Brackett’s Architecture
» Basic Architecture THE 3M SWITCH
» Cell Delineation Unit THE 3M SWITCH
» VCI-Overwrite Unit Cell Synchronization Unit
» Input and Output Forwarding Engines Input and Output Switch Interfaces
» Route Controller Router Module and Route Controller
» Input Optical Module Output Optical Module Tunable Filters
» Principles of Ping-Pong Arbitration Consider an N-input
» Performance of PPA Implementation of PPA
» Priority PPA Ping-Pong Arbitration Unit
» Component Complexity OIN Complexity
» Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
» Crosstalk Analysis OPTICAL INTERCONNECTION NETWORK FOR
» System Considerations WIRELESS ATM STRUCTURE OVERVIEWS
» NEC’s WATMnet Prototype System
» Olivetti’s Radio ATM LAN Virtual Connection Tree
» BAHAMA Wireless ATM LAN NTT’s Wireless ATM Access
» Radio Physical Layer RADIO ACCESS LAYERS
» Medium Access Control Layer Data Link Control Layer
» Connection Rerouting HANDOFF IN WIRELESS ATM
» Buffering Cell Routing in a COS
» Design of a Mobility-Support Switch
» Performance MOBILITY-SUPPORT ATM SWITCH
» Architectures of Generic Routers
» IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE IP ROUTE LOOKUP BASED ON STANDARD
» Levels 2 and 3 of Data Structure
» Adapting Binary Search for Best-Matching Prefix
» Precomputed 16-Bit Prefix Table Multiway Binary Search: Exploiting the Cache Line
» Lookup Algorithms and Data Structure Construction
» Prefix Update Algorithms IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
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