Performance of MSDA Switch

CROSSPOINT BUFFERED SWITCHES 236 Ž . Fig. 8.8 Low-priority selection rule. 䊚1999 IEEE. least one cell stored in each buffer or virtual queue. If the high- or low-priority transit buffers are about to become full, they send not-acknowl- edgments NACK H and NACK L, respectively, to the upper CNTL. ᎐ ᎐ The cell selection algorithm in the MSDA switch is as follows. If CNTL receives NACK dH from the lower high-priority transit buffer, neither a ᎐ high-priority cell nor a low-priority cell is transmitted. This is because, when the lower high-priority transit buffer is about to become full, there is no chance for the low-priority cell in the lower transit buffer to be transmitted. Low-priority cells cannot be transmitted when there is at least one high-prior- ity REQ from the crosspoint buffer and the transit buffer. When both the high-priority crosspoint buffer and the high-priority transit buffer send REQs to CNTL, the high-priority cell selection rule used is the cell selection rule used in the SSDA switch. Low-priority cells can be transmitted only when there are no REQs from either the high-priority crosspoint buffer or the high-priority transit buffer. If this condition is satisfied and CNTL does not receive either NACK H or ᎐ NACK L from the lower transit buffer, then the low-priority selection rule is ᎐ used. The low-priority crosspoint buffer and virtual queues in the low-priority transit buffer send REQs to CNTL as shown in Figure 8.8. Ring arbitration is executed at each crosspoint in a distributed manner. CNTL selects a cell and transmits it to the lower transit buffer. Thus the MSDA switch achieves distributed arbitration at each crosspoint. It uses the delay-time-based cell selection rule for the high-priority buffer and the distributed RR-based cell selection rule for the low-priority class.

8.3.2 Performance of MSDA Switch

The performance of the MSDA switch is described. It is assumed that, in an N = N crosspoint-buffered switch, input traffic for both the high- and low- priority classes is random, and cells are distributed uniformly to all crosspoint buffers belonging to the same input line. MULTIPLE-QOS SDA SWITCH 237 TABLE 8.1 Throughput in MSDA Switch Case 1 Input Load Throughput Inport Port High Low High Low 1 0.060 0.050 0.060 0.050 2 0.060 0.050 0.060 0.050 3 0.060 0.150 0.060 0.050 4 0.180 0.050 0.180 0.050 5 0.060 0.050 0.060 0.050 6 0.060 0.050 0.060 0.050 7 0.060 0.050 0.060 0.050 8 0.060 0.050 0.060 0.050 Total 0.600 0.500 0.600 0.400 TABLE 8.2 Throughput in MSDA Switch Case 2 Input Load Throughput Inport Port High Low High Low 1 0.060 0.030 0.060 0.030 2 0.060 0.030 0.060 0.030 3 0.060 0.400 0.060 0.190 4 0.180 0.030 0.180 0.030 5 0.060 0.030 0.060 0.030 6 0.060 0.030 0.060 0.030 7 0.060 0.030 0.060 0.030 8 0.060 0.030 0.060 0.030 Total 0.600 0.600 0.600 0.400 Since the high-priority is not influenced by, but does influence the low-pri- ority class, the results of the high-priority class are the same as those of the SSDA switch. Therefore, only the performance for the low-priority buffer is presented here. Tables 8.1 and 8.2 show that the MSDA switch keeps the fairness in terms of the throughput for the low-priority class. We present results for two traffic conditions, case 1 and case 2. The switch size was set to N s 8. In case 1, the high-priority load of the fourth input port is 0.18 and that of other input ports is 0.06. The low-priority load of the third input port is 0.15 and that of other input ports is 0.05, as shown in Table 8.1. The total input Ž . load is 1.1 0.6 q 0.5 , which is overloaded. The output load, which we call the throughput, for the high-priority class is the same as the high-priority input load for each input port. The low-priority throughput of all input ports is equally divided into 0.05 to utilize the residual bandwidth. Thus, the residual bandwidth is fairly shared with all the low-priority input traffic, although its requests for bandwidth are different. CROSSPOINT BUFFERED SWITCHES 238 In case 2, the low-priority load of the third input port is 0.4 and that of other input ports is 0.03, as shown in Table 8.2. The high-priority input load Ž . is the same as in case 1. The total input load is 1.2 0.6 q 0.6 , which is also overloaded. The low-priority throughput for input ports except for the third input port is 0.03, which is the same as the input load, and the low-priority throughput for the third input port is 0.19, which is larger than 0.03. The low-priority throughput is first equally divided into 0.03, which satisfies the input ports except for the third. Since some bandwidth remains, the residual bandwidth is given to the third input port. Therefore, the low-priority throughput of the third input port is 0.19. This means that the MSDA switch achieves max᎐min fair share for the low-priority class. REFERENCES 1. H. J. Chao, B.-S. Choe, J.-S Park, and N. Uzun, ‘‘Design and implementation of abacus switch: a scalable multicast ATM switch,’’ IEEE J. Selct. Areas Commun., vol. 15, no. 5, pp. 830᎐843, 1997. 2. E. Oki and N. Yamanaka, ‘‘Scalable crosspoint buffering ATM switch architecture using distributed arbitration scheme,’’ Proc. IEEE ATM ’97 Workshop, pp. 28᎐35, 1997. 3. E. Oki and N. Yamanaka, ‘‘A high-speed ATM switch based on scalable dis- tributed arbitration,’’ IEICE Trans. Commun., vol. E80-B, no. 9, pp. 1372᎐1376, 1997. 4. E. Oki, N. Yamanaka, and M. Nabeshima, ‘‘Scalable-distributed-arbitration ATM switch supporting multiple QoS classes,’’ Proc. IEEE ATM ’99 Workshop, 1999. 5. E. Oki, N. Yamanaka, and M. Nabeshima, ‘‘Performance of scalable-distributed- arbitration ATM switch supporting multiple QoS classes,’’ IEICE Trans. Commun., vol. E83-B, no. 2, pp. 204᎐213, 2000. 6. H. Tomonaga, N. Matsuoka, Y. Kato, and Y. Watanabe, ‘‘High-speed switching module for a large capacity ATM switching system,’’ Proc. IEEE GLOBECOM ’9 2, pp. 123᎐127, 1992. H. Jonathan Chao, Cheuk H. Lam, Eiji Oki Copyright 䊚 2001 John Wiley Sons, Inc. Ž . Ž . ISBNs: 0-471-00454-5 Hardback ; 0-471-22440-5 Electronic CHAPTER 9 THE TANDEM-CROSSPOINT SWITCH The HOL blocking problem in input-buffered switches can be eliminated by using the parallel-switch technique, where one switch fabric consists of multiple switch planes. The switch fabric operates at the line rate, and thus the arbitration timing is relaxed compared with the internal speedup switch architecture. However, the parallel-switch architecture suffers from a cell-out-of- sequence problem at output ports. A resequencing circuit needs to be implemented at the output ports to ensure that cells are delivered in order. For example, timestamps can be carried in the cell headers and stored at output buffers. Ž . w x A tandem-crosspoint TDXP switch 11, 12 developed by NTT has logi- cally multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. The TDXP switch achieves a high throughput without increasing the internal speed of switch fabric. It also preserves the cell-sequence order. The remainder of this chapter is as follows. Section 9.1 briefly reviews basic input and output buffered switch architectures. Section 9.2 presents the TDXP switch architecture. Section 9.3 shows its performance. Throughout Ž this chapter, we assume that the switch size is N = N N input ports and N . output ports . Input and output have the same line speed.

9.1 OVERVIEW OF INPUT