BASICS OF PACKET SWITCHING
22
Fig. 2.5 Classification of ATM switching architectures.
2.2.1 Time-Division Switching
In TDS, there is a single internal communication structure, which is shared by all cells traveling from input ports to output ports through the switch. The
internal communication structure can be a bus, a ring, or a memory. The main disadvantage of this technique is its strict capacity limitation of
the internal communication structure. However, this class of switch provides an advantage in that, since every cell flows across the single communica-
tion structure, it can easily be extended to support multicast
rbroadcast operations.
2.2.1.1 Shared-Medium Switch
In a shared-medium switch, cells arriv- ing at input ports are time-division multiplexed into a common high-speed
medium, such as a bus or a ring, of bandwidth equal to N times the input line rate. The throughput of this shared medium determines the capacity of
the entire switch. As shown in Figure 2.6, each output line is connected to the shared high-speed medium via an interface consisting of an address filter
Ž
. AF and an output FIFO buffer. The AF examines the header part of the
incoming cells, and then accepts only the cells destined for itself. This decentralized approach has an advantage in that each output port can
operate independently and can be built separately. However, more hardware logic and more buffers are required to provide the separate interface for
each output port.
A time slot is divided into N mini-slots. During each mini-slot, a cell from an input is broadcast to all output ports. This simplifies the multicasting
process. A bit map of output ports with each bit indicating if the cell is routed to that output port can be attached to the front of the cell. Each AF
will examine only the corresponding bit to decide if the cell should be stored
SWITCH ARCHITECTURE CLASSIFICATION
23
Fig. 2.6 Shared-medium switching architecture.
in the following FIFO. One disadvantage of this structure is that the switch size N is limited by the memory speed. In particular, when all N input cells
are destined for the same output port, the FIFO may not be able to store all N cells in one time slot if the switch size is too large or the input line rate is
too high. Another disadvantage is the lack of memory sharing among the FIFO buffers. When an output port is temporarily congested due to high
traffic loading, its FIFO buffer is filled and starts to discard cells. Meanwhile, other FIFO buffers may have plenty of space but cannot be used by the
congested port. As a result, a shared-memory switch, as described below, has a better buffer utilization.
Ž Examples of shared-medium switches are NEC’s ATOM ATM output
. w x
Ž buffer modular switch 13 , IBM’s PARIS packetized automated routing
. w x
integrated system switch 2 , and Fore System’s ForeRunner ASX-100 switch w x
3 . 2.2.1.2
Shared-Memory Switch In a shared-memory switch, as shown in
Figure 2.7, incoming cells are time-division multiplexed into a single data stream and sequentially written to the shared memory. The routing of cells is
accomplished by extracting stored cells to form a single output data stream, which is in turn demultiplexed into several outgoing lines. The memory
addresses for both writing incoming cells and reading out stored cells are provided by a control module according to routing information extracted
from the cell headers.
The advantage of the shared-memory switch type is that it provides the best memory utilization, since all input
routput ports share the same mem- ory. The memory size should be adjusted accordingly to keep the cell loss
rate below a chosen value. There are two different approaches in sharing
BASICS OF PACKET SWITCHING
24
Fig. 2.7 Basic architecture of shared-memory switches.
memory among the ports: complete partitioning and full sharing. In complete partitioning, the entire memory is divided into N equal parts, where N is the
number of input routput ports, and each part is assigned to a particular
output port. In full sharing, the entire memory is shared by all output ports without any reservation. Some mechanisms, such as putting an upper and a
lower bound on the memory space, are needed to prevent monopolization of the memory by some output ports.
Like shared-medium switches, shared-memory switches have the disadvan- tage that the memory access speed limits the switch size; furthermore, the
control in the shared-memory switches is more complicated. Because of its better buffering utilization, however, the shared-memory type is more popu-
lar and has more variants than the shared-medium type. Detailed discussions about those variants and their implementations are given in Chapter 4.
Examples of shared-memory switches are Toshiba’s 8 = 8 module on a w x
w x single chip 12 and Hitachi’s 32 = 32 module 8 .
2.2.2 Space-Division Switching
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