THE ABACUS SWITCH
222
Fig. 7.25 Delay performance of a packet switch with packet interleaving.
with an arrival time. When the last cell of a packet leaves the output buffer, the packet is timestamped with a departure time. The difference between the
arrival time and the departure time is defined as the packet delay. When Ž
. there is no internal speedup S s 1 in the switch fabric, the delay perfor-
mance of the packet interleaving switch is very poor, mainly due to the HOL blocking. The delay᎐throughput performance is improved by increasing the
Ž .
speedup factor S e.g., S s 2 . Note that the input buffer’s average delay is much smaller than the output buffer’s average delay. With an internal
speedup of two, the output buffer’s average delay dominates the total average delay and is very close to that of the output-buffered switch.
7.7.2 Cell Interleaving
A packet switch using a cell interleaving technique is shown in Figure 7.26. Arriving cells are stored in the input buffer until the last cell of a packet
arrives. Once the last cell arrives, cells are transferred in the same way as in an ATM switch. That is, cells from different input ports can be interleaved
ABACUS SWITCH FOR PACKET SWITCHING
223
Fig. 7.26
A packet switch with cell interleaving.
with each other as they arrive at the output port. Cells have to carry input port numbers so that output ports can distinguish them from different
packets. Therefore, each output port has N reassembly buffers, each corre- sponding to an input port. When the last cell of a packet arrives at the
reassembly buffer, all cells belonging to the packet are moved to the output buffer for transmission to the output link. In real implementation, only
w x pointers are moved, not the cells. This architecture is similar the one in 17
in the sense that they both use reassembly buffers at the outputs, but it is w x
more scalable than the one in 17 . The operation speed of the abacus switch fabric is limited to several
hundred megabits per second with state-of-the-art CMOS technology. To Ž
accommodate the line rate of a few gigabits per second e.g., Gigabit
. Ethernet and OC-48 , we can either use a bit-slice technique or the one
shown in Figure 7.26, where the high-speed cell stream is distributed to m one-cell buffers at each input port. The way of dispatching cells from the IPC
to the m one-cell buffers is identical to dispatching cells from the ISC to the
Ž . M one-cell buffers in Figure 7.21 c . The advantage of the technique in
Figure 7.26 over the bit-slice technique is its smaller overhead bandwidth: the latter shrinks the cell duration while keeping the same overhead for each
cell.
Figure 7.27 shows the average packet delay vs. offered load for a packet Ž
. switch with cell interleaving. When there is no internal speedup S s 1 , the
delay performance is poor. With an internal speedup S of two, the delay
THE ABACUS SWITCH
224
Fig. 7.27 Delay performance of a packet switch with cell interleaving.
performance is close to that of an output-buffered packet switch. By compar- ing the delay performance between Figure 7.25 and Figure 7.27, we can see
that the average delay performance is comparable. However, we believe that the delay variation of cell interleaving will be smaller than that of packet
interleaving because of its finer granularity in switching.
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H. Jonathan Chao, Cheuk H. Lam, Eiji Oki Copyright 䊚 2001 John Wiley Sons, Inc.
Ž .
Ž .
ISBNs: 0-471-00454-5 Hardback ; 0-471-22440-5 Electronic
CHAPTER 8
CROSSPOINT-BUFFERED SWITCHES
When more than one cell is contending for the limited link capacity inside a switch or at its outputs, buffers are provided to temporarily store the cells.
Since the size of a buffer is finite, cells will be discarded when it is full. However, in previous chapters we have described several switch architectures
Ž .
with input buffering, output buffering including shared memory , input and output buffering, and internal buffering in a multistage structure.
This chapter describes crosspoint-buffered switches, where each cross- point has a buffer. This switch architecture takes advantage of today’s CMOS
technology, where several millions of gates and several tens of millions of bits can be implemented on the same chip. Furthermore, there can be several
hundred input and output signals operating at 2᎐3 Gbitrs on one chip. This switch architecture does not require any increase of the internal line speed. It
eliminates the HOL blocking that occurs in the input-buffered switch, at the cost of having a large amount of crosspoint-buffer memory at each cross-
point.
The remainder of this chapter is organized as follows. Section 8.1 de- scribes a basic crosspoint-buffered switch architecture. The arbitration time
among crosspoint buffers can become a bottleneck as we increase the switch Ž
. size. Section 8.2 introduces a scalable distributed-arbitration SDA switch to
avoid the bottleneck of the arbitration time. Section 8.3 describes an ex- tended version of SDA to support multiple QoS classes.
227
CROSSPOINT BUFFERED SWITCHES
228
Fig. 8.1 Crosspoint-buffered switch structure based on round-robin arbitration.
8.1 OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES
