The Staggering Switch ALL-OPTICAL PACKET SWITCHES

ALL-OPTICAL PACKET SWITCHES 281

11.1 ALL-OPTICAL PACKET SWITCHES

In optical packet switches, logical control and contention resolution are handled by an electronic controller, and packets are carried and stored in optical memories. There are two kinds of optical memory used in all-optical packet switches: one is the traveling type based on fiber delay lines, and the other is the fiber-loop type where packets carried at different wavelengths coexist in the fiber loop.

11.1.1 The Staggering Switch

w x The staggering switch 9 is one of the optically transparent switches. The major components of the switch are splitter detectors, rearrangeable non- blocking switches, and a control unit. The switch architecture is based on two stages: the scheduling stage and the switching stage, as shown in Figure 11.1. These two stages can be considered as rearrangeably nonblocking networks. The scheduling stage and the switching stage are of size N = M and M = N, respectively, where M is less than N. These two stages are connected by a set of optical delay lines having unequal delay. The idea behind this architecture is to arrange incoming cells in the scheduling stage in such a way that there will be no output port collision in the switching stage. This is achieved by holding the cells that cause output port collision on the delay lines. The delay on the delay line d is equal to i cell slots. The arrangement of incoming cells i Ž . Fig. 11.1 Block diagram of the staggering switch. 䊚 1993 IEEE. OPTICAL PACKET SWITCHES 282 is accomplished electronically by the control unit according to the output port requests of incoming cells. When a cell arrives at the switch, its header information is converted into an electrical signal and sent to the control unit by the corresponding splitter detector. After evaluating the current destination requests considering the previous requests, the control unit sends the information related to the current schedule to the scheduling stage. The cell is routed through the scheduling stage with respect to the information sent by the control unit. Due to the statistical properties of the incoming cells, it is possible to lose some cells in the scheduling stage. After waiting for a certain period of time on the assigned delay line, the cell reaches the switching stage. No contention occurs in the switching stage, on account of the precautions taken by the control unit, and the cell reaches the requested output port. In this architecture, cells arriving at the same input port may arrive at output ports in the reverse order, since they are assigned to different delay lines. Ordered delivery of cells at the output ports can be achieved by some additional operations in the control unit. The main bottleneck in this switch architecture is the control unit. The proposed collision resolution algorithm is too complicated to handle large switch size or high input line rate. Some input buffers may be necessary in order to keep newly arriving cells while the control unit makes its arrange- ments.

11.1.2 ATMOS