Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
2.3.2 Output-Buffered Switches
With output queuing, cells are only buffered at outputs, at each of which a Ž . separate FIFO is maintained. Consider a particular i.e., tagged output queue. Define the random variable A as the number of cell arrivals destined for the tagged output in a given time slot. Based on the same assumptions as in Section 2.3.1 on the arrivals, we have k N yk p p N w x a J Pr A s k s 1 y , k s 0, 1, 2, . . . N 2.9 Ž . k ž ž ž k N N Ž . When N ™ ⬁, 2.9 becomes p k e yp w x a J Pr A s k s , k s 0, 1, 2, . . . . 2.10 Ž . k k Denote by Q the number of cells in the tagged queue at the end of the m mth time slot, and by A the number of cell arrivals during the mth time m slot. We have Q s min max 0, Q q A y 1 , b . 2.11 4 Ž . Ž . m m y1 m PEFORMANCE OF BASIC SWITCHES 41 If Q s 0 and A 0, there is no cell waiting at the beginning of the m y1 m mth time slot, but we have A cells arriving. We assume that one of the m arriving cells is immediately transmitted during the mth time slot; that is, a cell goes through the switch without any delay. For finite N and finite b, this can be modeled as a finite-state, discrete-time w x Markov chain with state transition probabilities P J Pr Q s j Q s i i j m m y1 as follows: a q a , i s 0, j s 0, ° 1 a , 1 F i F b, j s i y 1, ~ a , 1 F j F b y 1, 0 F i F j, P s 2.12 Ž . j yiq1 i j N Ý a , j s b, 0 F i F j, m sjyiq1 m ¢ otherwise , Ž . Ž . where a is given by 2.9 and 2.10 for a finite N and N ™ ⬁, respectively. k The steady-state queue size can be obtained recursively from the following Markov chain balance equations: 1 y a y a 1 w x q J Pr Q s 1 s ⭈ q 1 a n 1 y a a 1 k w x q J Pr Q s n s ⭈ q y ⭈ q , 2 F n F b, Ý n n y1 n yk a a k s2 where 1 w x q J Pr Q s 0 s ⭈ b 1 q Ý q rq n s1 n No cell will be transmitted on the tagged output line during the mth time slot if, and only if, Q s 0 and A s 0. Therefore, the switch throughput m y1 m is represented as s 1 y q a ⭈ A cell will be lost if, when emerging from the switch fabric, it finds the output buffer already containing b cells. The cell loss probability can be calculated as follows: w x Pr cell loss s 1 y , p where p is the offered load. BASICS OF PACKET SWITCHING 42 Fig. 2.17 The cell loss probability for output queuing as a function of the buffer size Ž . Ž . b and the switch size N, for offered loads a p s 0.8 and b p s 0.9. PEFORMANCE OF BASIC SWITCHES 43 Ž . Ž . Figure 2.17 a and b show the cell loss probability for output queuing as a function of the output buffer size b for various switch size N and offered loads p s 0.8 and 0.9. At the 80 offered load, a buffer size of b s 28 is good enough to keep the cell loss probability below 10 y6 for arbitrarily large N. The N ™ ⬁ curve can be a close upper bound for finite N 32. Figure 2.18 shows the cell loss performance when N ™ ⬁ against the output buffer size b for offered loads p varying from 0.70 to 0.95. Output queuing achieves the optimal throughput᎐delay performance. Cells are delayed unless it is unavoidable, when two or more cells arriving on different inputs are destined for the same output. With Little’s result, the mean waiting time W can be obtained as follows: b Q Ý nq n s1 n W s s . 1 y q a Figure 2.19 shows the numerical results for the mean waiting time as a function of the offered load p for N ™ ⬁ and various values of the output buffer size b. When N ™ ⬁ and b ™ ⬁, the mean waiting time is obtained from the M rDr1 queue as follows: p W s . 2 1 y p Ž . Fig. 2.18 The cell loss probability for output queuing as a function of the buffer size b and offered loads varying from p s 0.70 to p s 0.95, for the limiting case of N ™ ⬁. BASICS OF PACKET SWITCHING 44 Fig. 2.19 The mean waiting time for output queuing as a function of the offered load p, for N ™ ⬁ and output FIFO sizes varying from b s 1 to ⬁.2.3.3 Completely Shared-Buffer Switches
Parts
» ATM Switch Structure ATM SWITCH SYSTEMS
» DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
» Internal Link Blocking Output Port Contention Head-of-Line Blocking
» Shared-Medium Switch Time-Division Switching
» Single-Path Switches Space-Division Switching
» Multiple-Path Switches Space-Division Switching
» Internally Buffered Switches Recirculation Buffered Switches
» Input- and Output-Buffered Switches Virtual-Output-Queueing Switches
» Input-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Completely Shared-Buffer Switches PERFORMANCE OF BASIC SWITCHES
» Bernoulli Arrival Process and Random Traffic On–Off Model and Bursty Traffic
» Multiline Input Smoothing Speedup Parallel Switch
» Window-Based Lookahead Selection Increasing Scheduling Efficiency
» VOQ-Based Matching Increasing Scheduling Efficiency
» Parallel Iterative Matching PIM Iterative Round-Robin Matching iRRM
» Iterative Round-Robin with SLIP i SLIP
» Dual Round-Robin Matching DRRM
» Round-Robin Greedy Scheduling SCHEDULING ALGORITHMS
» Bidirectional Arbiter Design of Round-Robin Arbiters r
» Token Tunneling This section introduces a more efficient arbi-
» Most-Urgent-Cell-First Algorithm MUCFA OUTPUT-QUEUING EMULATION
» Critical Cell First CCF Last In, Highest Priority LIHP
» LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST JONATHAN CHAO CHEUK LAM
» LINKED LIST APPROACH JONATHAN CHAO CHEUK LAM
» CONTENT-ADDRESSABLE MEMORY APPROACH JONATHAN CHAO CHEUK LAM
» Washington University Gigabit Switch
» Shared-Memory Switch with a Multicast Logical Queue Shared-Memory Switch with Cell Copy
» Shared-Memory Switch with Address Copy
» BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
» Three-Phase Implementation Ring Reservation
» BATCHER-SORTING NETWORK THE SUNSHINE SWITCH
» Tandem Banyan Switch DEFLECTION ROUTING
» Shuffle-Exchange Network with Deflection Routing
» Dual Shuffle-Exchange Network with Error-Correcting Routing
» Generalized Self-Routing Algorithm Broadcast Banyan Network
» Boolean Interval Splitting Algorithm Nonblocking Condition of Broadcast Banyan Networks A
» Encoding Process MULTICAST COPY NETWORKS
» Concentration Decoding Process Overflow and Call Splitting
» A. Cyclic Running Adder Network Figure 5.34 shows the struc-
» Concentration The starting point in a CRAN may not be port 0,
» Basic Architecture SINGLE-STAGE KNOCKOUT SWITCH
» Knockout Concentration Principle SINGLE-STAGE KNOCKOUT SWITCH
» Construction of the Concentrator
» Maximum Throughput CHANNEL GROUPING PRINCIPLE
» Two-Stage Configuration A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Multicast Grouping Network A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Translation Tables A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Cross-Stuck CS Fault Toggle-Stuck TS Fault Verticalr
» Toggle-Stuck and Cross-Stuck Cases
» Vertical-Stuck and Horizontal-Stuck Cases
» Cross-Stuck and Toggle-Stuck Cases
» Vertical-Stuck Case Horizontal-Stuck SWE Case
» APPENDIX JONATHAN CHAO CHEUK LAM
» BASIC ARCHITECTURE JONATHAN CHAO CHEUK LAM
» MULTICAST CONTENTION RESOLUTION ALGORITHM
» IMPLEMENTATION OF INPUT PORT CONTROLLER
» Cell Loss Probability PERFORMANCE
» ATM ROUTING AND CONCENTRATION CHIP
» Memoryless Multistage Concentration Network
» Buffered Multistage Concentration Network
» Resequencing Cells ENHANCED ABACUS SWITCH
» Complexity Comparison ENHANCED ABACUS SWITCH
» Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» Cell Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» MSDA Structure MULTIPLE-QOS SDA SWITCH
» OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES OVERVIEW OF INPUT
» Basic Architecture Unicasting Operation
» ROUTING PROPERTIES AND SCHEDULING METHODS
» A SUBOPTIMAL STRAIGHT MATCHING METHOD
» Basic Architecture Distributed and Random Arbitration
» Basic Architecture THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
» Concurrent Round-Robin Dispatching Scheme
» Homogeneous Capacity and Route Assignment
» The Staggering Switch ALL-OPTICAL PACKET SWITCHES
» HYPASS OPTOELECTRONIC PACKET SWITCHES
» STAR-TRACK OPTOELECTRONIC PACKET SWITCHES
» Cisneros and Brackett’s Architecture
» Basic Architecture THE 3M SWITCH
» Cell Delineation Unit THE 3M SWITCH
» VCI-Overwrite Unit Cell Synchronization Unit
» Input and Output Forwarding Engines Input and Output Switch Interfaces
» Route Controller Router Module and Route Controller
» Input Optical Module Output Optical Module Tunable Filters
» Principles of Ping-Pong Arbitration Consider an N-input
» Performance of PPA Implementation of PPA
» Priority PPA Ping-Pong Arbitration Unit
» Component Complexity OIN Complexity
» Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
» Crosstalk Analysis OPTICAL INTERCONNECTION NETWORK FOR
» System Considerations WIRELESS ATM STRUCTURE OVERVIEWS
» NEC’s WATMnet Prototype System
» Olivetti’s Radio ATM LAN Virtual Connection Tree
» BAHAMA Wireless ATM LAN NTT’s Wireless ATM Access
» Radio Physical Layer RADIO ACCESS LAYERS
» Medium Access Control Layer Data Link Control Layer
» Connection Rerouting HANDOFF IN WIRELESS ATM
» Buffering Cell Routing in a COS
» Design of a Mobility-Support Switch
» Performance MOBILITY-SUPPORT ATM SWITCH
» Architectures of Generic Routers
» IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE IP ROUTE LOOKUP BASED ON STANDARD
» Levels 2 and 3 of Data Structure
» Adapting Binary Search for Best-Matching Prefix
» Precomputed 16-Bit Prefix Table Multiway Binary Search: Exploiting the Cache Line
» Lookup Algorithms and Data Structure Construction
» Prefix Update Algorithms IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
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