APPENDIX
185
Figure 6.33 shows the cell loss rates of inputs of the switch module with a Ž
. HS SWE. The cell loss rates of all inputs above the faulty one i s 35 are
equal to those of fault-free L s 11 case, while the faulty input has no cell loss. The cell loss rates of the inputs below the faulty one are almost equal to
those of the fault-free L s 11 case, because one of j output links is always occupied by the cells from the faulty input, and they are independent of the
faulty input’s cell arrival pattern.
From the above analysis it can be concluded that under the single-fault condition, the worst cell loss performance degradation corresponds to the
loss of one output link. Note that these cell loss rates are not the average rate of the entire MOBAS but that of the SM with a faulty SWE. When an input
experiences cell loss performance degradation due to a faulty SWE, it corresponds to one output link loss in the worst case. Thus, if we add one
more column of SWEs for each switch module, which corresponds to less than 2 hardware overhead in MGN1 and less than 9 hardware overhead
in MGN2, under any kind of single-fault condition, the MOBAS can still have as good cell loss performance as the originally designed, fault-free
system.
6.5 APPENDIX
Let us consider an ATM switch as shown in Figure 6.10, and assume that cells arrive independently from different input ports and are uniformly
delivered to all output ports. The variables used are defined as follows.
N: the number of a switch’s input ports or output ports M: the number of output ports that are in the same group
L: the group expansion ratio
: the offered load of each input port, or the average number of cells that arrive at the input port in each cell time slot
rN: the average number of cells from each input port destined for an output port in each cell time slot
MrN: the number of cells from each input port destined for an output
group in each cell time slot P : the probability that k cells arrive at an output group in each cell time
k
slot
: the average number of cells from all input ports that are destined for an output group in each cell time slot
X
: the average number for cells from all input ports that have arrived at an output group in each cell time slot
KNOCKOUT-BASED SWITCHES
186
Then P is given by the following binomial probability:
k k
Nyk
M
M
N P s
1 y ,
k s 0, 1, . . . , N,
k
ž
ž ž
k N
N and we have
N
M
s kP s N
s M,
Ý
k
ž
N
ks1 LM
N
X
s kP q
LM P
Ž .
Ý Ý
k k
ks1 ksLMq1
N N
s y kP q
LM P
Ž .
Ý Ý
k k
ksLMq1 ksLMq1
N
s y k y LM P .
Ž .
Ý
k
ksLMq1
Since at most LM cells are sent to each output group in each cell time slot, the excess cells will be discarded and lost. The cell loss probability is
y
X
P cell loss s
Ž .
N
1 s
k y LM P
Ž .
Ý
k
ksLMq1
k Nyk
N
1
M
M N
s k y LM
1 y .
6.15
Ž .
Ž .
Ý
ž
ž ž
k
M N
N
ksLMq1
As N ™ ⬁,
k y M
M
e
Ž .
P s ,
k
k
k y M
⬁
1
M e
Ž .
P cell loss s k y LM
Ž .
Ž .
Ý
M
k
ksLMq1
k y M
⬁
k y LM
M e
Ž . Ž
.
s
Ý
M
k
ksLMq1
REFERENCES
187
ky1 k
y M y M
⬁ ⬁
M
e L
M
e
Ž .
Ž .
s y
Ý Ý
k y 1
k
Ž .
ksLMq1 ksLMq1
k k
y M y M
⬁ ⬁
M
e L
M
e
Ž .
Ž .
s y
Ý Ý
k
k
ksLM ksLMq1
L M k
y M y M
⬁
M
e
M e
Ž .
Ž .
s q
Ý
LM k
Ž .
ksLMq1
k y M
⬁
L
M e
Ž .
y
Ý
k
ksLMq1
k L M
y M y M
⬁
L
M e
M
e
Ž .
Ž .
s 1 y q
Ý
ž
ž
k
LM
Ž .
ksLMq1
k L M
y M y M
LM
L
M e
M
e
Ž .
Ž .
s 1 y 1 y
q .
6.16
Ž .
Ý
ž
ž
k
LM
Ž .
ks0
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H. Jonathan Chao, Cheuk H. Lam, Eiji Oki Copyright 䊚 2001 John Wiley Sons, Inc.
Ž .
Ž .
ISBNs: 0-471-00454-5 Hardback ; 0-471-22440-5 Electronic
CHAPTER 7
THE ABACUS SWITCH
The switches based on the knockout concept suffer from cell loss due to the lack of routing links in the switch fabricᎏfor example, the concentrator in
Ž .
the knockout switch, or the multicast grouping network MGN in the
MOBAS in Chapter 6. Although we can engineer the group expansion ratio L to achieve a satisfactory cell loss probability, say 10
y10
, that is based on the assumption that the traffic from different input ports is uncorrelated and
input traffic is uniformly distributed to all output ports. The latter assump- tion gives the worst case cell loss probability, while the former assumption
may not be realistic for the applications such as Internet Web services. There may be a lot of traffic destined for the same popular site at the same time,
resulting in a so-called hot-spot situation and an unacceptable cell loss probability. In order to reduce the cell loss rate, excess cells can be stored at
the input buffers, which results in the switch having buffers at the input and output ports. The switch to be discussed in this chapter belongs to this
category.
We describe a switch that has a similar architecture to the MOBAS but Ž
. does not discard cells in the switch fabric. When the head-of-line HOL cells
of the input ports are sent to the switch fabric, they are held at the input ports until they have been successfully transmitted to the desired output port.
The switch fabric is a crossbar structure, where switch elements, with the capability of routing cells and resolving contention based on cells’ priority
levels, are arranged in a two-dimensional array, and is similar to an abacus. For this reason it is called the abacus switch. The challenging issue of
designing an input᎐output-buffered switch is to design a fast and scalable arbitration scheme.
189
THE ABACUS SWITCH
190
The arbitration algorithm proposed in the abacus switch takes advantage of the switch element’s ability to resolve contention for the routing links
according to their priority levels. As a result, with some extra feedback lines and logic circuits at the input ports, the arbitration scheme can be imple-
mented without adding much complexity and cost. The switch uses a new arbitration scheme to resolve the contention among the HOL cells. The
arbitration is done in a distributed manner and thus enables the switch to grow to a large size.
Section 7.1 describes the basic architecture of the abacus switch. Section 7.2 presents the new arbitration scheme, which is implemented in a dis-
tributed manner. Section 7.3 depicts the implementation of an input con- troller and how it resolves contention resolution. Section 7.4 discusses the
performance of the abacus in throughput, delay, and loss. Section 7.5 shows a
Ž .
key component, the ATM routing and concentration ARC chip used to implement the abacus switch. Section 7.6 describes three approaches to scale
the abacus switch to 1-Tbitrs capacity. Section 7.7 shows how the abacus switch can also route switch packets through the switch fabric.
7.1 BASIC ARCHITECTURE
