DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
13
Differences between ATM switches and IP routers systems lie in their line cards. Therefore, both ATM switch systems and IP routers can be con-
structed by using a common switch fabric with appropriate line cards.
1.3 DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
Several design criteria need to be considered when designing a packet switch architecture. First, the switch should provide bounded delay and small cell
loss probability while achieving a maximum throughput close to 100. Capability of supporting high-speed input lines is also an important criterion
for multimedia services, such as video conferencing and videophone. Self- routing and distributed control are essential to implement large-scale
switches. Serving packets based on first come, first served provides correct packet sequence at the output ports. Packets from the same connection need
to be served in sequence without causing out of order.
Bellcore has recommended performance requirements and objectives for Ž
. w x broadband switching systems BSSs
3 . As shown in Table 1.1, three QoS classes and their associated performance objectives are defined: QoS class 1,
QoS class 3, and QoS class 4. QoS class 1 is intended for stringent cell loss applications, including the circuit emulation of high-capacity facilities such as
DS3. It corresponds to service class A, defined by ITU-T study group XIII. QoS class 3 is intended for low-latency, connection-oriented data transfer
applications, corresponding to service class C in ITU-T study group XIII. QoS Class 4 is intended for low-latency, connectionless data transfer applica-
tion, corresponding to service class D in ITU-T study group XIII.
The performance parameters used to define QoS classes 1, 3, and 4 are Ž
. cell loss ratio, cell transfer delay, and two-point cell delay variation CDV .
The values of the performance objectives corresponding to a QoS class Ž
. Ž
depend on the status of the cell loss priority CLP bit CLP s 0 for high
TABLE 1.1 Performance Objective across BSS for ATM Connections Delivering
Cells to an STS-3c or STS-12c Interface
Performance Parameter CLP
QoS 1 QoS 3
QoS 4
y 10
y 7
y 7
Cell loss ratio - 10
- 10 - 10
a
Cell loss ratio 1
NrS NrS
NrS
b
Ž .
Cell transfer delay 99th percentile 1r0
150 s 150 s
150 s
y 10
Ž .
Cell delay variation 10 quantile
1r0 250 s
NrS NrS
y 7
Ž .
Cell delay variation 10 quantile
1r0 NrS
250 s 250 s
a
NrS not specified.
b
Includes nonqueuing related delays, excluding propagation. Does not include delays due to processing above ATM layer.
INTRODUCTION
14
Fig. 1.8 Distribution of cell transfer delay.
. priority, and CLP s 1 for low priority , which is initially set by the user and
can be changed by a BSS within the connection’s path. Figure 1.8 shows a typical distribution of the cell transfer delay through a
switch node. The fixed delay is attributed to the delay of table lookup and Ž
. other cell header processing, such as header error control HEC byte
examination and generation. For QoS classes 1, 3, and 4, the probability of Ž
. cell transfer delay CTD greater than 150 s is guaranteed to be less than
w x
1 y 0.99, that is, Prob CTD 150 s - 1 y 99. For this requirement, a s 1 and x s 150 s in Figure 1.8. The probability of CDV greater
than 250 s is required to be less than 10
y 10
for QoS class 1, that is, w
x
y 10
Prob CDV 250 s - 10 .
REFERENCES
1. N. McKeown, ‘‘A fast switched backplane for a gigabit switched router,’’ Business Commun. Re®., vol. 27, no. 12, Dec. 1997.
2. X. Xiao and L. M. Ni, ‘‘Internet QoS: a big picture,’’ IEEE Network, pp. 8᎐18, MarchrApril 1999.
Ž .
3. Bellcore, ‘‘Broadband switching system BSS generic requirements, BSS perfor- mance,’’ GR-110-CORE, Issue 1, Sep. 1994.
H. Jonathan Chao, Cheuk H. Lam, Eiji Oki Copyright 䊚 2001 John Wiley Sons, Inc.
Ž .
Ž .
ISBNs: 0-471-00454-5 Hardback ; 0-471-22440-5 Electronic
CHAPTER 2
BASICS OF PACKET SWITCHING
This chapter discusses the basic concepts in designing an ATM switch. An ATM switch has multiple inputroutput ports, each connecting to another
port of an ATM switch or an ATM terminal. An ATM terminal can be a personal computer, a workstation, or any other equipment that has an ATM
Ž .
network interface card NIC . The physical layer of interconnecting ATM Ž
switches or ATM terminals can be SONET such as OC-3c, OC-12c, OC-48, .
Ž .
or OC-192 or others such as T1 or T3 . Physical layer signals are first terminated and cells are extracted for further processing, such as table
lookup, buffering, and switching. Cells from different places arrive at the input ports of the ATM switch. They are delivered to different output ports
according to their labels, merged with other cell streams, and put into physical transmission frames. Due to the contention of multiple cells from
different input ports destined for the same output port simultaneously, some cells must be buffered while the other cells are transmitted to the
output ports. Thus, routing cells to the proper output ports and buffering them when they lose contention are the two major functions of an ATM
switch.
Traditional telephone networks use circuit switching techniques to estab- lish connections. In the circuit switching scheme, there is usually a central-
ized processor that determines all the connections between input and output ports. Each connection lasts on average 3 min. For an N = N switch, the
time required to make each connection is 180 seconds divided by N. For instance, suppose N is 1000. The connection time is 180 ms, which is quite
relaxed for most of switch fabrics using current technology, such as CMOS crosspoint switch chips. However, for ATM switches, the time needed to
15
BASICS OF PACKET SWITCHING
16
configure the input routput connections is much more stringent, because it is
based on the cell time slot. For instance, for the OC-12c interface, each cell slot time is about 700 ns. For an ATM switch with 1000 ports, the time to
make the connection for each input routput is 700 ps, which is very challeng-
ing for existing technology. Furthermore, as the line bit rate increases Ž
. e.g., with OC-48c and the number of the switch ports increases, the time
needed for each connection is further reduced. As a result, it is too expensive to employ centralized processors for ATM switches.
Thus, for ATM switches we do not use a centralized connection processor to establish connections. Rather, a self-routing scheme is used to establish
input routput connections in a distributed manner. In other words, the switch
fabric has the ability to route cells to proper output ports, based on the physical output port addresses that are attached in the front of each cell.
One switch fabric that has self-routing capability is called the banyan switch. It will be discussed in more detail in Chapter 5.
In addition to the routing function to the ATM switch, another important function is to resolve the output port contention when more than one cell is
destined for the same output port at the same time. There are several contention-resolution schemes that have been proposed since the first ATM
Ž switch architecture was proposed in early 1980s the original packet switch
was called a high-speed packet switch; the term ATM was not used until late .
1980 . One way to resolve the contention is to allow all cells that are destined for the same output port to arrive at the output port simultaneously. Since
only one cell can be transmitted via the output link at a time, most cells are queued at the output port. A switch with such architecture is called an
output-buffered switch. The price to pay for such scheme is the need for operating the switch fabric and the memory at the output port at a rate N
times the line speed. As the line speed or the switch port number increases, this scheme can have a bottleneck. However, if one does not allow all cells to
go to the same output port at the same time, some kind of scheduling scheme, called an arbitration scheme, is required to arbitrate the cells that are
destined for the same output port. Cells that lose contention will need to wait at the input buffer. A switch with such architecture is called an input-buffered
switch.
The way of handling output contention will affect the switch performance, complexity, and implementation cost. As a result, most research on ATM
switch design is devoted to output port contention resolution. Some schemes are implemented in a centralized manner, and some in a distributed manner.
The latter usually allows the switch to be scaled in both line rate and switch size, while the former is for smaller switch sizes and is usually less complex
and costly.
In addition to scheduling cells at the inputs to resolve the output port contention, there is another kind of scheduling that is usually implemented at
the output of the switch. It schedules cell or packet transmission according to
SWITCHING CONCEPTS
