Priority PPA Ping-Pong Arbitration Unit
11.4.5.4 Priority PPA
Among the packets contending for the same out- put, those from real-time sessions are more delay-sensitive than the others from non-real-time sessions, so they should have higher priority. Therefore, Ž . sessions and thus their packets with various QoS requirements need to be OPTICAL PACKET SWITCHES 322 Ž . Fig. 11.37 Decomposition of arbitration delay in an AR256. 䊚1999 IEEE. assigned different levels of service priority. Below it is shown how to enhance the PPA for handling priority. Two priority representations are used in our design for transfer efficiency and arbitration convenience, respectively. Suppose p levels of priority are Ž supported. An input has altogether p q 1 states including the case of no . u Ž .v request , which can be represented by using log p q 1 bits. The interlayer 2 request information could be transferred either in series using one line or in parallel using multiple lines, depending on the tradeoff chosen between delay and pin count complexity. The serial᎐parallel format transformation can be realized by using shift registers. A group of p lines is used in the second representation. At most one of them is HIGH, indicating that there is one request at the corresponding level of priority. There will be no request if all output lines are LOW. OPTICAL INTERCONNECTION NETWORK FOR TERABIT IP ROUTERS 323 Fig. 11.38 Demonstration of priority handling with parallel arbitration: seven prior- ity levels and 16 inputs. Our solution to multipriority arbitration relies on a group of parallel single-priority arbiters to resolve the contention at each level of priority simultaneously. Multiple single-priority arbiters are necessary to maintain the Ž . arbitration states states of the flip-flops for each level of priority, which will be changed only when an input request at this priority level is granted. A preprocessing phase and a postprocessing phase are then added, as demonstrated in Figure 11.38, with a multipriority arbiter, which handles 16 inputs and seven levels of priority. A decoder is used at each input to decode the three-line priority request into seven single lines, each representing the request in the corresponding level of priority and entering the corresponding arbiter for single-priority contention resolution. An OR gate is used at each output to combine all corresponding local grants from the single-priority arbiters to produce the final grants for each input. Meanwhile, every single-priority arbiter generates a group request signal for the upper layer’s arbitration; it receives a group grant signal later, which Ž . indicates if this group of requests at the corresponding level of priority is granted or not. A priority encoder collects all the group requests from the OPTICAL PACKET SWITCHES 324 single-priority arbiters and indicates among them the highest priority with its three-line output. The outputs, in addition to being forwarded to the upper layer, will also be used to inhibit the arbiters with lower priority from producing any active grants. A decoder with its outputs masked by the upper-layer grant signal is used to decompose the output of the priority encoder into seven single-line grant signals, each for a single-priority arbiter. Only the arbiter at the corresponding level of priority will receive the upper layer’s grant signal, while all the others will receive nothing but a LOW grant signal.11.4.6 OIN Complexity
Parts
» ATM Switch Structure ATM SWITCH SYSTEMS
» DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
» Internal Link Blocking Output Port Contention Head-of-Line Blocking
» Shared-Medium Switch Time-Division Switching
» Single-Path Switches Space-Division Switching
» Multiple-Path Switches Space-Division Switching
» Internally Buffered Switches Recirculation Buffered Switches
» Input- and Output-Buffered Switches Virtual-Output-Queueing Switches
» Input-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Completely Shared-Buffer Switches PERFORMANCE OF BASIC SWITCHES
» Bernoulli Arrival Process and Random Traffic On–Off Model and Bursty Traffic
» Multiline Input Smoothing Speedup Parallel Switch
» Window-Based Lookahead Selection Increasing Scheduling Efficiency
» VOQ-Based Matching Increasing Scheduling Efficiency
» Parallel Iterative Matching PIM Iterative Round-Robin Matching iRRM
» Iterative Round-Robin with SLIP i SLIP
» Dual Round-Robin Matching DRRM
» Round-Robin Greedy Scheduling SCHEDULING ALGORITHMS
» Bidirectional Arbiter Design of Round-Robin Arbiters r
» Token Tunneling This section introduces a more efficient arbi-
» Most-Urgent-Cell-First Algorithm MUCFA OUTPUT-QUEUING EMULATION
» Critical Cell First CCF Last In, Highest Priority LIHP
» LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST JONATHAN CHAO CHEUK LAM
» LINKED LIST APPROACH JONATHAN CHAO CHEUK LAM
» CONTENT-ADDRESSABLE MEMORY APPROACH JONATHAN CHAO CHEUK LAM
» Washington University Gigabit Switch
» Shared-Memory Switch with a Multicast Logical Queue Shared-Memory Switch with Cell Copy
» Shared-Memory Switch with Address Copy
» BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
» Three-Phase Implementation Ring Reservation
» BATCHER-SORTING NETWORK THE SUNSHINE SWITCH
» Tandem Banyan Switch DEFLECTION ROUTING
» Shuffle-Exchange Network with Deflection Routing
» Dual Shuffle-Exchange Network with Error-Correcting Routing
» Generalized Self-Routing Algorithm Broadcast Banyan Network
» Boolean Interval Splitting Algorithm Nonblocking Condition of Broadcast Banyan Networks A
» Encoding Process MULTICAST COPY NETWORKS
» Concentration Decoding Process Overflow and Call Splitting
» A. Cyclic Running Adder Network Figure 5.34 shows the struc-
» Concentration The starting point in a CRAN may not be port 0,
» Basic Architecture SINGLE-STAGE KNOCKOUT SWITCH
» Knockout Concentration Principle SINGLE-STAGE KNOCKOUT SWITCH
» Construction of the Concentrator
» Maximum Throughput CHANNEL GROUPING PRINCIPLE
» Two-Stage Configuration A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Multicast Grouping Network A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Translation Tables A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Cross-Stuck CS Fault Toggle-Stuck TS Fault Verticalr
» Toggle-Stuck and Cross-Stuck Cases
» Vertical-Stuck and Horizontal-Stuck Cases
» Cross-Stuck and Toggle-Stuck Cases
» Vertical-Stuck Case Horizontal-Stuck SWE Case
» APPENDIX JONATHAN CHAO CHEUK LAM
» BASIC ARCHITECTURE JONATHAN CHAO CHEUK LAM
» MULTICAST CONTENTION RESOLUTION ALGORITHM
» IMPLEMENTATION OF INPUT PORT CONTROLLER
» Cell Loss Probability PERFORMANCE
» ATM ROUTING AND CONCENTRATION CHIP
» Memoryless Multistage Concentration Network
» Buffered Multistage Concentration Network
» Resequencing Cells ENHANCED ABACUS SWITCH
» Complexity Comparison ENHANCED ABACUS SWITCH
» Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» Cell Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» MSDA Structure MULTIPLE-QOS SDA SWITCH
» OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES OVERVIEW OF INPUT
» Basic Architecture Unicasting Operation
» ROUTING PROPERTIES AND SCHEDULING METHODS
» A SUBOPTIMAL STRAIGHT MATCHING METHOD
» Basic Architecture Distributed and Random Arbitration
» Basic Architecture THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
» Concurrent Round-Robin Dispatching Scheme
» Homogeneous Capacity and Route Assignment
» The Staggering Switch ALL-OPTICAL PACKET SWITCHES
» HYPASS OPTOELECTRONIC PACKET SWITCHES
» STAR-TRACK OPTOELECTRONIC PACKET SWITCHES
» Cisneros and Brackett’s Architecture
» Basic Architecture THE 3M SWITCH
» Cell Delineation Unit THE 3M SWITCH
» VCI-Overwrite Unit Cell Synchronization Unit
» Input and Output Forwarding Engines Input and Output Switch Interfaces
» Route Controller Router Module and Route Controller
» Input Optical Module Output Optical Module Tunable Filters
» Principles of Ping-Pong Arbitration Consider an N-input
» Performance of PPA Implementation of PPA
» Priority PPA Ping-Pong Arbitration Unit
» Component Complexity OIN Complexity
» Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
» Crosstalk Analysis OPTICAL INTERCONNECTION NETWORK FOR
» System Considerations WIRELESS ATM STRUCTURE OVERVIEWS
» NEC’s WATMnet Prototype System
» Olivetti’s Radio ATM LAN Virtual Connection Tree
» BAHAMA Wireless ATM LAN NTT’s Wireless ATM Access
» Radio Physical Layer RADIO ACCESS LAYERS
» Medium Access Control Layer Data Link Control Layer
» Connection Rerouting HANDOFF IN WIRELESS ATM
» Buffering Cell Routing in a COS
» Design of a Mobility-Support Switch
» Performance MOBILITY-SUPPORT ATM SWITCH
» Architectures of Generic Routers
» IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE IP ROUTE LOOKUP BASED ON STANDARD
» Levels 2 and 3 of Data Structure
» Adapting Binary Search for Best-Matching Prefix
» Precomputed 16-Bit Prefix Table Multiway Binary Search: Exploiting the Cache Line
» Lookup Algorithms and Data Structure Construction
» Prefix Update Algorithms IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
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