Crosspoint-Buffered Switches Input-Buffered Switches Output-Buffered Switches Multistage Shared-Buffer Switches

SWITCH ARCHITECTURE CLASSIFICATION 35 buffers are used to store internally blocked cells so that the cell loss rate can be reduced. Scalability of the switch can be easily achieved by replicating the SEs. However, this type of switch suffers from low throughput and high transfer delay that is caused by the delay from multiple stages. To meet QoS requirements, some scheduling and buffer management schemes need to be installed at the internal SEs, which will increase the implementation cost.

2.2.3.2 Recirculation Buffered Switches

This type of switch is pro- posed to overcome the output port contention problem. As shown in Figure Ž . 2.15 b , the switch consists of both input routput ports and special ports called recirculation ports. When output port contention occurs, the switch allows the successful cell to go to the output port. Cells that have lost the contention are stored in a recirculation buffer and try again in the next time slot. In order to preserve the cell sequence, a priority value is assigned to each cell. In each time slot, the priority level of the cells losing contention is increased by one so that these cells will have a better chance to be selected in the next time slot. If a cell has reached its highest priority level and the cell still has not gotten through, it will be discarded to avoid out-of-sequence errors. The number of recirculation ports can be engineered to achieve accept- able cell loss rate. For instance, it has been shown that to achieve a cell loss rate of 10 y6 at 80 load and Poisson arrivals, the ratio of recirculation ports w x to input ports must be 2.5. The Starlite switch 6 is an example of this type of switch. The number of recirculation ports can be reduced dramatically by allowing more than one cell to arrive at the output port in each time slot. It has been shown that for a cell loss probability of 10 y6 at 100 load and Poisson arrivals, the ratio of the recirculation ports to the input ports is reduced to w x 0.1 by allowing three cells arriving at each output port. The Sunshine 4 switch is an example of this switch type.

2.2.3.3 Crosspoint-Buffered Switches

This type of switch, as shown in Ž . Figure 2.15 c , is the same as the crossbar-based switch discussed in Section 2.2.2.

2.2.3.4 Input-Buffered Switches

The input-buffered switch, as shown in Ž . Figure 2.15 d , suffers from the HOL blocking problem and limits the throughput to 58.6 for uniform traffic. In order to increase the switch’s throughput, a technique called windowing can be employed, where multiple cells from each input buffer are examined and considered for transmission to the output port. But at most one cell will be chosen in each time slot. The number of examined cells determines the window size. It has been shown that by increasing the window size to two, the maximum throughput is increased to 70. Increasing the window size does not improve the maximum BASICS OF PACKET SWITCHING 36 throughput significantly, but increases the implementation complexity of input buffers and arbitration mechanism. This is because the input buffers cannot use simple FIFO memory any longer, and more cells need to be arbitrated in each time slot. Several techniques have been proposed to increase the throughput and are discussed in detail in Chapter 3.

2.2.3.5 Output-Buffered Switches

The output-buffered switch, shown Ž . in Figure 2.15 e , allows all incoming cells to arrive at the output port. Because there is no HOL blocking, the switch can achieve 100 throughput. However, since the output buffer needs to store N cells in each time slot, its memory speed will limit the switch size. A concentrator can be used to alleviate the memory speed limitation problem so as to have a larger switch size. The disadvantage of this remedy is the inevitable cell loss in the concentrator. Ž . 2.2.3.6 Shared-Buffer Switches Figure 2.15 f shows the shared buffer switch, which will be discussed in detail in Chapter 4.

2.2.3.7 Multistage Shared-Buffer Switches

The shared-buffer architec- ture has been widely used to implement small-scale switches because of its high throughput, low delay, and high memory utilization. Although a large- scale switch can be realized by interconnecting multiple shared-buffer switch Ž . modules, as shown in Figure 2.15 g , the system performance is degraded due to the internal blocking. Due to different queue lengths in the first- and second-stage modules, maintaining cell sequence at the output module can be very complex and expensive.

2.2.3.8 Input- and Output-Buffered Switches