A FAULT-TOLERANT MULTICAST OUTPUT-BUFFERED ATM SWITCH
183
Ž .
Fig. 6.32
Cell loss rate of each input port after cross-reconfiguration. 䊚1994 IEEE.
Ž . The probability P A is considered as the cell loss rate improvement of the
k th input Figure 6.32 shows the cell loss rate of each input after the SWE array is
reconfigured. Here, the MOBAS is assumed to be a single stage with a size of 64 = 64 and an expansion ratio L of 12. The faulty SWE is assumed to be
Ž .
Ž .
SWE 35, 12 . For those inputs above the faulty input 35 , the cell loss rates are the same as in the fault-free case, while the faulty input’s cell loss rate is
equal to that of the L s 11 fault-free case. The inputs below the faulty one Ž
. from 36 to 64 have almost the same cell loss rates as in the fault-free case,
Ž . since the improvement P A is very small.
6.4.4.2 Vertical-Stuck Case
When there is a VS SWE in the jth column, all the SWEs in that column are forced to a cross state to isolate the jth
Ž .
column, as shown in Figure 6.29 j s 2 . This column isolation prevents cells from being corrupted, but reduces available routing links from L to L y 1.
Therefore, after the reconfiguration, the cell loss rate of each input is slightly increased to the following:
P
X
k s P k ,
1 F k F N.
Ž . Ž .
L Ly1
Note that the effect on the cell loss performance degradation is independent of the faulty link’s position. The cell loss rates after the reconfiguration are
KNOCKOUT-BASED SWITCHES
184
equal to those of the fault-free L s 11 case, regardless of the row position of the faulty link.
6.4.4.3 Horizontal-Stuck SWE Case
Figure 6.31 shows a reconfiguration Ž
. Ž
. example of HS SWE 4, 2 . Let us consider an HS i, j case: the cell loss rates
Ž .
of all inputs above the ith one are equal to those of the fault-free L y 1 case, while the ith input has no cell loss. And the cell loss rates of all inputs
Ž .
below the ith one are almost equal to those of the fault-free L y 1 case. Incoming cells from all inputs above the ith one can only be routed to L y 1
Ž output links, and the ith input always occupies one of j output links from
. the first to the jth .
Special attention is needed when we consider the cell loss rates of the Ž
. inputs below the ith row. The cell loss rate of the k th input i - k F N
depends only on k y 2 inputs, which are all above the kth one and exclude the ith input. Thus, the cell loss rate of the k th input is equal to that of the
Ž .
k y 1 th input in the case where the switch module is fault-free and its expansion ratio is L y 1:
°
P k ,
1 F k - i y 1,
Ž .
Ly1 X
~
P k s
Ž .
0, k s i,
L
¢
P k y 1 ,
i q 1 F k F N.
Ž .
Ly1
Fig. 6.33 Cell loss rate of each input port after partial column isolation.
APPENDIX
185
Figure 6.33 shows the cell loss rates of inputs of the switch module with a Ž
. HS SWE. The cell loss rates of all inputs above the faulty one i s 35 are
equal to those of fault-free L s 11 case, while the faulty input has no cell loss. The cell loss rates of the inputs below the faulty one are almost equal to
those of the fault-free L s 11 case, because one of j output links is always occupied by the cells from the faulty input, and they are independent of the
faulty input’s cell arrival pattern.
From the above analysis it can be concluded that under the single-fault condition, the worst cell loss performance degradation corresponds to the
loss of one output link. Note that these cell loss rates are not the average rate of the entire MOBAS but that of the SM with a faulty SWE. When an input
experiences cell loss performance degradation due to a faulty SWE, it corresponds to one output link loss in the worst case. Thus, if we add one
more column of SWEs for each switch module, which corresponds to less than 2 hardware overhead in MGN1 and less than 9 hardware overhead
in MGN2, under any kind of single-fault condition, the MOBAS can still have as good cell loss performance as the originally designed, fault-free
system.
6.5 APPENDIX
Let us consider an ATM switch as shown in Figure 6.10, and assume that cells arrive independently from different input ports and are uniformly
delivered to all output ports. The variables used are defined as follows.
N: the number of a switch’s input ports or output ports M: the number of output ports that are in the same group
L: the group expansion ratio
: the offered load of each input port, or the average number of cells that arrive at the input port in each cell time slot
rN: the average number of cells from each input port destined for an output port in each cell time slot
MrN: the number of cells from each input port destined for an output
group in each cell time slot P : the probability that k cells arrive at an output group in each cell time
k
slot
: the average number of cells from all input ports that are destined for an output group in each cell time slot
X
: the average number for cells from all input ports that have arrived at an output group in each cell time slot
