Route Controller Router Module and Route Controller

OPTICAL PACKET SWITCHES 308 data FIFO and checks if it is the first segment of a packet. If not, the current MP is used for the segment. If so, the IPC gets a new MP from the MP FIFO and repeats the procedure. Upon being transmitted in the OIN, each segment is marked with a number identifying the input port in order to facilitate packet reassembly at the outputs. At each OSI, data segments from the OIN are stored in the data segment memory, which is organized as linked lists connecting all segments of each packet as in a shared-memory switch. There is an idle-pointer FIFO keeping the unused memory pointers. A separate pointer memory indexed by the input port number is used to store the head and tail pointers of the linked lists of the packets being transmitted over the OIN to the output. Once all segments of a packet have arrived, the entire linked list is completed and the Ž . segment header processor SHP will forward its head pointer to the head pointer FIFO for packet departure scheduling. The head and tail pointers of the packet, which are no longer necessary, will be deleted from the pointer memory to prepare for the next packet arrival from the same input port. The Ž . head pointer FIFO keeps the packets in the order of their last segments’ Ž . arrival times. The packet reassembly unit PRU fetches the HOL packet and schedules its segment transmission.

11.4.3.3 Route Controller

The RC in the router performs three main Ž . Ž . tasks: 1 executing routing protocols such as RIP and DVMRP and other Ž . control protocols such as ICMP, IGMP, and SNMP , exchanging control messages via the RMs with neighbor routers and network management Ž . Ž . servers, and maintaining a routing information base RIB in the system; 2 based on the RIB, computing, updating, and distributing the IP unicast or w Ž .x multicast forwarding table also called the forwarding information base FIB Ž . for every RM; and 3 performing packet filter management. All the commu- nications are through a control plane, which can be implemented either by a specific bus, such as a PCI bus, or by the core switch, such as the OIN. Ž . Because trace data collected from a major Internet service provider ISP backbone router indicate that a few hundred updates can occur per second in w x the worst case, with an average of 1.04 updates per second 50 , the RC needs to perform fast FIB updates. These include the operations of inserting a new route entry, modifying an old entry with new information such as new or Ž . additional outgoing interface s for this route, and removing an old entry due to timeout or route changes. Besides, since FIBs are usually organized in a treelike data structure in order to facilitate fast searching, changing a single route can affect a large number of relevant entries in an FIB. Many FIBs are to be updated if they all have this route entry. To resolve the above challenge, it is suggested to let the RC directly access to each FIB rather than periodically download the full table to each RM, especially when there are only minor changes in the table. Consider the w x unicast case. Suppose each table size is 32 Mbyte 50 . The width of a PCI OPTICAL INTERCONNECTION NETWORK FOR TERABIT IP ROUTERS 309 bus is 64 bits, its frequency is 66 MHz. Simply downloading all 2 = 256 tables will take about 31 seconds, which is unacceptably large. On the other hand, multiple RCs can be arranged in a hierarchical way to provide load balancing. One of the RCs can be responsible for maintaining a common RIB shared by the others in the system. Each RC will handle a number of RMs and this number depends on the processing power of the RC Ž . and the bandwidth of the interconnection i.e., control plane between the RCs and the RMs. The traffic on the control plane include routing informa- tion, network control messages, FIB updates, packet filter management messages, and other local hardware monitoring and diagnosis messages. Another challenge is to design an efficient control structure for intercon- necting the RCs and the RMs. One can either separate the control plane and data plane or let both share a common plane, such as the OIN, where control traffic should have higher priority than data. The advantage of using separate planes is to reduce the complexity of switch interconnection management and to improve the data throughput performance. Besides, the router will have better scalability in that the design of control plane and data plane can be optimized separately.

11.4.4 Optical Interconnection Network