INPUT-BUFFERED SWITCHES
78
depart during the second phase. Similarly, cells B-3 and C-4 must depart w
Ž .x during the fourth and sixth phases, respectively see Fig. 3.22 b . Continuing
w Ž .
Ž .x this elimination process see Fig. 3.22 c and d , there is only one possible
scheduling order. For this input traffic pattern, the switch needs all seven
7
phases in four time slots, which corresponds to a minimum speedup of
4 1
Ž .
or 2 y . The proof of the general case for an N = N switch is a straight-
4
forward extension of the 4 = 4 example.
3.5 LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST
ALGORITHM LOOFA
w x
The LOOFA is a work-conserving scheduling algorithm 16 . It provides 100 throughput and a cell delay bound for feasible traffic, using a speedup
of 2. An input᎐output-queued architecture is considered. Two versions of this scheme have been presented: the greedy and the best-first. This scheme
considers three different parameters associated with a cell, say cell c, to perform a match: the number of cells in its destined output queue, or output
Ž . Ž .
occupancy, OCC c ; the timestamp of a cell, or cell age, TS c ; and the smallest port number, to break ties. Under the speedup of 2, each time slot
has two phases. During each phase, the greedy ®ersion of this algorithm works Ž
. as follows see Fig. 3.23 for an example :
1. Initially, all inputs and outputs are unmatched. Ž
2. Each unmatched input selects an active VOQ i.e., a VOQ that has at .
least one cell queued going to the unmatched output with the lowest
Fig. 3.23 A matching example with the greedy LOOFA.
LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST ALGORITHM LOOFA
79
occupancy, and sends a request to that output. Ties are broken by Ž .
selecting the smallest output port number. See Figure 3.23 a . 3. Each output, on receiving requests from multiple inputs, selects the one
with the smallest OCC and sends the grant to that input. Ties are broken by selecting the smallest port number.
4. Return to step 2 until no more connections can be made. An example of the greedy version is shown in Figure 3.23. The tuple X, Y
Ž . in the VOQ represents the output occupancy OCC c and the timestamp
Ž . TS c of cell c, respectively. In the upper part of the figure, the arrows
indicate the destinations for all different cells at the input ports. The gray arrows in the lower part of the figure indicate the exchange of requests and
Ž . grants. The black arrows indicate the final match. Part a shows that each
input sends a request to the output with the lowest occupancy. Output 2 receives two requests, one from A and the other from B, while output 3
Ž . receives a request from input C. Part b illustrates that, between the two
requests, output 2 chooses input A, the one with lower TS. Output 3 chooses the only request, input C.
The best-first version works as follows: 1. Initially, all inputs and outputs are unmatched.
2. Among all unmatched outputs, the output with the lowest occupancy is selected. Ties are broken by selecting the smallest output port number.
All inputs that have a cell destined for the selected output send a request to it.
3. The output selects the cell request input with the smallest time stamp and sends the grant to the input. Ties are broken by selecting the
smallest input port number. Ž
4. Return to step 2 until no more connections can be made or N .
iterations are completed . Figure 3.24 shows a matching example with the best-first version. The
Ž . selection of the output with the lowest OCC c results in a tie: Outputs 2 and
3 have the lowest OCC. This tie is broken by selecting output 2, since this port number is the smaller. Therefore, inputs A and B send a request to this
Ž . Ž .
output as shown in part b , while part c illustrates that output 2 grants the Ž .
oldest cell, input A. Part d shows the matching result after the first Ž .
iteration. The second iteration begins in part e when output 3 is chosen as the unmatched output port with the lowest OCC with requests from inputs B
Ž . Ž .
Ž . and C. Input B is chosen in part f for its lowest TS c . Part g depicts the
final match. Both algorithms achieve a maximal matching, with the greedy version
achieving it in less iterations. On the other hand, it has been proven that, when combined with the oldest-cell-first input selection scheme, the best-first
INPUT-BUFFERED SWITCHES
80
Fig. 3.24 A matching example with the best-first version of LOOFA.
version provides delay bounds for rate-controlled input traffic under a speedup of 2. Denote by D and D the arbitration delay and the output
a o
Ž .
queuing delay of any cell. It can be shown that that D F 4 Nr S y 1 and
a
D F 2 N cell slots, where S is the speedup factor.
o
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H. Jonathan Chao, Cheuk H. Lam, Eiji Oki Copyright 䊚 2001 John Wiley Sons, Inc.
Ž .
Ž .
ISBNs: 0-471-00454-5 Hardback ; 0-471-22440-5 Electronic
CHAPTER 4
SHARED-MEMORY SWITCHES
In shared-memory switches, all input and output ports have access to a common memory. In every cell time slot, all input ports can store incoming
Ž .
cells and all output ports can retrieve their outgoing cells if any . A
shared-memory switch works essentially as an output-buffered switch, and therefore also achieves the optimal throughput and delay performance.
Furthermore, for a given cell loss rate, a shared-memory switch requires less buffers than other switches.
Because of centralized memory management to achieve buffer sharing, however, the switch size is limited by the memory readrwrite access time,
within which N incoming and N outgoing cells in a time slot need to be accessed. As shown in the formula given below, the memory access cycle
must be shorter than 1r2 N of the cell slot, which is the transmission time of a cell on the link:
cell length memory access cycle F
. 2 ⭈ N ⭈ link speed
Ž For instance, with a cell slot of 2.83 s 53-byte cells at the line rate of
. 149.76 Mbitrs, or 155.52 Mbitrs = 26r27 and with a memory cycle time of
10 ns, the switch size is limited to 141. Several commercial ATM switch systems based on the shared memory
architecture provide a capacity of several tens of gigabits per second. Some people may argue that memory density doubles every 18 months and so the
memory saving by the shared-memory architecture is not that significant. However, since the memory used in the ATM switch requires high speed
83
SHARED-MEMORY SWITCHES
84
Ž .
e.g., 5᎐10-ns cycle time , it is expensive. Thus, reducing the total buffer size can considerably reduce the implementation cost. Some shared-
memory switch chip sets have the capability of integrating with other space Ž
switches to build a large-capacity switch e.g., a few hundred gigabits per .
second . Although the shared-memory switch has the advantage of saving buffer
size, the buffer can be occupied by one or a few output ports that are congested and thus leave no room for other cells destined for other output
ports. Thus, there is normally a cap on the buffer size that can be used by any output port.
The following sections discuss different approaches to organize the shared memory and necessary control logics. The basic idea of the shared-memory
switch is to use logical queues to link the cells destined for the same output port. Section 4.1 describes this basic concept, the structure of the logical
queues, and the pointer processing associated with writing and reading cells to and from the shared memory. Section 4.2 describes a different approach to
implement the shared-memory switch by using a content-addressable memory Ž
. Ž
. CAM instead of a random access memory RAM as in most approaches.
Although CAM is not as cost-effective and fast as RAM, the idea of using CAM to implement the shared-memory switch is interesting because it
eliminates the need of maintaining logical queues. The switch size is limited by the memory chip’s speed constraint, but several approaches have been
proposed to increase it, such as the space᎐time᎐space approach in Section 4.3 and multistage shared-memory switches in Section 4.4. Section 4.5 de-
scribes several shared-memory switch architectures to accommodate multi- casting capability.
4.1 LINKED LIST APPROACH
