SWITCH ARCHITECTURE CLASSIFICATION
25
SDS switches are classified based on the number of available paths between any input
routput pair. In single-path switches, only one path exists for any input
routput pair, while in multiple-path switches there is more than one. The former has simpler routing control than the latter, but the latter has
higher fault tolerance.
2.2.2.1 Single-Path Switches
Single path switches are classified into crossbar-based switches,
fully interconnected switches, and banyan-based w x
switches 10 . a Crossbar Switches
A crossbar switch is schematically shown in Figure 2.8 for N
s 4, where horizontal lines represent the inputs to the switch, and vertical lines represent the outputs. Basically, an N = N crossbar switch
consists of a square array of N
2
individually operated crosspoints, one corresponding to each input᎐output pair. Each crosspoint has two possible
Ž .
states: cross default and bar. A connection between input port i and output Ž
. port j is established by setting the i, j th crosspoint switch to the bar state
while letting other crosspoints along the connection remain the cross state. The bar state of a crosspoint can be triggered individually by each incoming
Fig. 2.8 A 4 = 4 crossbar switch.
BASICS OF PACKET SWITCHING
26
cell when its destination matches with the output address. No global informa- tion about other cells and their destinations is required. This property is
called the self-routing property; by it the control complexity is significantly reduced in the switching fabric, as the control function is distributed among
all crosspoints.
Crossbar switches have three attractive properties: they are internally nonblocking, simple in architecture, and modular. However, they are complex
in terms of the number of the crosspoints, which grows as N
2
. The arbitra- tion that is to choose a winner for every output in each time slot can also
become a system bottleneck as the switch size increases. Ž .
There are three possible locations for the buffers in a crossbar switch: a Ž .
Ž . at the crosspoints in the switch fabric, b at the inputs of the switch, and c
at the inputs and outputs of the switch. Each one has its advantages and disadvantages.
Ž . Figure 2.9 a depicts the strategy of buffering cells at the crosspoints. The
Ž .
bus matrix switch BMX proposed by Fujitsu is an example of this type of w x
switch 11 . There is an AF and a buffer at each crosspoint. The AF accepts the cells destined for the corresponding output port and stores them in the
buffer. Cells waiting in the buffers on the same column are arbitrated to the output port with one cell per slot. The switch is work-conserving, and does
not suffer the throughput limitation incurred with input buffering. In a sense, it is similar to achieving output queuing, with the difference that the queue
for each output is distributed over N buffers. As there is no sharing among the N buffers, the total memory required for a given loss rate is greater than
Ž .
that required for output queuing e.g., in the shared-medium case . As the buffer memory typically requires much more real estate in a chip than
crosspoint logic, including the crosspoint buffers in the chip would severely limit the number of crosspoints in the chip.
Ž . Figure 2.9 b depicts the input queuing approach. Separating the buffers
from the crosspoints is desirable from the viewpoint of layout and circuit compactness. A cell arriving at an input first enters the buffer, waiting its
turn to be switched over the fabric. With distributed contention resolution, conflicts are resolved individually at crosspoints. When a cell reaches a
crosspoint that has already been set by an earlier cell, or it loses contention to another contending cell, a blocking signal is generated and sent to the
input port. This is to block the transmission of the cell and to keep the cell in the input buffer for later tries. With centralized contention resolution,
alternatively, an arbiter is used for each output port to resolve contention, and only one cell destined for an output is allowed to be forwarded to the
switch fabric.
The third approach combines the advantages of input buffering and output buffering. The detail is described in Section 2.2.3.
b Fully Interconnected Switches In a fully interconnected switch, the
complete connectivity between inputs and outputs is usually accomplished by
SWITCH ARCHITECTURE CLASSIFICATION
27
Fig. 2.9 Different buffering strategies for a crossbar switch.
BASICS OF PACKET SWITCHING
28
Fig. 2.10 A fully interconnected switch.
means of N separate broadcast buses from every input port to all output ports, as shown in Figure 2.10. N separate buffers are required in such a
switch, one at each output port. However, if each of these N output buffers in the fully interconnected switch is partitioned and dedicated to each input
line, yielding N
2
dedicated buffers, it becomes topologically identical with the crosspoint-buffered switch, and thus provides exactly the same perfor-
mance and implementation complexity. The fully interconnected switch operates in a similar manner to the
shared-medium switch. A cell from any input port is broadcast to every output port. Thus, cells from several input ports can be simultaneously
transmitted to the same output port. Therefore, cell filters and dedicated buffers, one for each output port, are required to filter out the misdelivered
cells and to temporarily store the properly destined cells.
However, the fully interconnected switch is different from the shared- medium switch in that the speedup overhead requirement caused by sequen-
tial transmission over the shared medium is replaced by the space overhead requirement of the N
2
separate broadcast buses. This is considered a disadvantage of the switch type. The advantages of the fully interconnected
switch lie in its simple and nonblocking structure, similar to the crossbar-based w x
switch. The knockout switch is an example of this type of switch 15 . c Banyan-Based Switches
Banyan-based switches are a family of self- routing switches constructed from 2 = 2 switching elements with a single
path between any input᎐output pair. As shown in Figure 2.11, there are
SWITCH ARCHITECTURE CLASSIFICATION
29
Fig. 2.11 Three different topologies of banyan-based switches.
three isomorphic topologiesᎏdelta, omega, and banyan networksᎏbelonging to the banyan-based family. All of them offer equivalent performance and
are discussed in detail in Chapter 5. The banyan-based switch provides several advantages: First, it has a
complexity of paths and switching elements of order N log N, which makes it much more suitable than the crossbar-based and the fully interconnected
switch, whose complexity is of order N
2
, for the construction of large switches. Self-routing is also an attractive feature in that no control mecha-
nism is needed for routing cells. Routing information is contained within each cell, and it is used while the cell is routed along the path. Parallel
structure of the switch provides a benefit in that several cells on different paths can be processed simultaneously. Due to their modular and recursive
structure, large-scale switches can be built by using elementary switching elements without modifying their structures. This can be appropriately real-
ized by VLSI implementation.
The main drawback of the banyan-based switch is that it is an internally blocking switch. Its performance degrades rapidly as the size of the switch
Ž .
increases. The performance may be improved if M = M M 2 switching elements are employed instead of 2 = 2 switching elements. This leads to the
class of delta-based switches. The delta-based switch is a family of self-routing switches constructed
from M = M switching elements with a single path between any input and output port. While the performance of the delta-based switch can be signifi-
cantly better than that of the banyan-based switch, it is still a blocking switch. The performance of the switch is reduced due to internal contention. This
can be improved by increasing the speed of internal links within the switch with respect to that of input and output ports or by introducing buffers into
the switching elements.
2.2.2.2 Multiple-Path Switches
