CLOS-NETWORK SWITCHES
274
Fig. 10.14 Route scheduling in central modules for the second example of uniform
Ž .
traffic. 䊚1997 IEEE.
pairs in one time slot assignment. Nevertheless, the total number of central modules assigned to every input᎐output pair within a frame should be the
same for uniform input traffic to fulfill the capacity requirement, and that number is equal to g s fmrk. This point is illustrated in the following
example. For m s 4 and k s 6, we choose f s 3 and g s 2. The same method will result in the connection patterns shown in Figure 10.14. It is easy
Ž .
to verify that the number of central modules paths, edges assigned for each input᎐output pair is equal to g s 2 per f s 3 slots.
10.5.2 Heterogeneous Capacity Assignment
The capacity assignment in a cross-path switch is virtual-path-based. It depends on the traffic load on each virtual path to allocate the capacity and
determine the route assignment. The Latin square offers a legitimate capac- ity assignment with homogeneous traffic, but it may no longer be effective
Ž with heterogeneous traffic nonuniformly distributed traffic load over the
. virtual paths . A more general assignment method is therefore introduced,
and the procedure is illustrated in Figure 10.15. The assignment procedure has four steps, each of which will be explained along with an example in the
following sub-subsections.
10.5.2.1 Virtual Path Capacity Allocation VPCA
This step is to allo- cate capacity to each virtual path based on the traffic loads. It can be
formulated as an optimization problem with some traffic modeling.
THE PATH SWITCH
275
Fig. 10.15 Procedure of capacity and route assignment.
Consider the cross-path switch with parameters n s 3, k s 3, and m s 4. Suppose the traffic matrix is given by
1 1
1
T s ,
10.8
Ž .
2 1
1 1
and the capacity assignment matrix calculated by the minimization of input- stage delay with MrDr1 model is
1.34 1.28
1.38
C s .
10.9
Ž .
2.66 1.34
1.38 2.62
10.5.2.2 The Roundoff Procedure Some elements in the resulting ca-
pacity matrix may be nonintegers. When they are rounded to the integers required in the route assignment, roundoff error arises. The concept of frame
size is used to reduce the roundoff error. Each element in the capacity matrix is multiplied by the frame size; then the capacity per slot is translated into
capacity per frame. After that, we round the matrix into an integer matrix:
1.34 1.28
1.38 4.02
3.84 4.14
Ž .
= fs 3
6
Cs 2.66 1.34
7.98 3.82
1.38 2.62
4.14 7.86
4 4
4
rounding
6
s E .
10.10
Ž .
8 4
4 8
CLOS-NETWORK SWITCHES
276
The roundoff error is inversely proportional to f. Thus, the error can be arbitrary small if the frame size is sufficiently large. However, since the
amount of routing information stored in the memory is linearly proportional to f, the frame size is limited by the access speed and the memory space of
input modules. In practice, the choice of frame size f is a compromise between the roundoff error and the memory requirement. In general,
e e
⭈⭈⭈ e
0 , 0 0 , 1
0 , ky1
e e
⭈⭈⭈ e
1 , 0 1 , 1
1 , ky1
. .
. E s
f f C
, .
. .
. .
. .
. .
e e
⭈⭈⭈ e
ky1 , 0 ky1 , 1
ky1 , ky1
and e s
e s fm. 10.11
Ž .
Ý Ý
i j i j
j i
In the above matrix E, each element e represents the number of the edges
i j
between the input module i and output module j in the k = k capacity graph, in which each node has degree fm.
10.5.2.3 Edge Coloring
As mentioned previously, this capacity graph can be colored by fm colors, and each color represents one distinct time᎐space
Ž .
slot based on the time᎐space interleaving principle 10.7 . Coloring can be found by complete matching, which is repeated recursively to reduce the
degree of every node one by one. One general method to search for a complete matching is the so-called Hungarian algorithm or alternating-path
w x
algorithm 9, 12 . It is a sequential algorithm with worst time complexity Ž
2
. Ž
2
. O k , or totally O fm = k
because there are fm matchings. If each of fm
Ž . Ž
.
Fig. 10.16 Route scheduling example heterogeneous traffic . 䊚1997 IEEE.
REFERENCES
277
w x and k is a power of two, an efficient parallel algorithm proposed in 7 for
conflict-free route scheduling in a three-stage Clos network with time com- Ž
2
Ž ..
plexity of O log fmk
can be used. Through the time᎐space interleaving, the middle-stage routing pattern in Figure 10.16 is obtained.
REFERENCES
1. H. J. Chao and J.-S. Park, ‘‘Centralized contention resolution schemes for a large-capacity optical ATM switch,’’ Proc. IEEE ATM Workshop-97, Fairfax, VA,
May 1998. 2. H. J. Chao , ‘‘Saturn: a terabit packet switch using dual round-robin,’’ IEEE
Commun. Mag., vol. 38, no. 12, pp.78᎐84, Dec. 2000. 3. K. Y. Eng and A. S. Acampora, ‘‘Fundamental conditions governing TDM
switching assignments in terrestrial and satellite networks,’’ IEEE Trans. Com- mun., vol. 35, pp. 755᎐761, Jul. 1987.
Ž .
4. K. Y. Eng, M. J. Karol, and Y.-S. Yeh, ‘‘A growable packet ATM switch architecture: design principles and applications,’’ IEEE Trans. Commun., vol. 40,
no. 2, pp. 423᎐430, Feb. 1992. 5. M. J. Karol and C.-L. I, ‘‘Performance analysis of a growable architecture for
Ž .
broadband packet ATM
switching,’’ Proc. IEEE GLOBECOM ’89, pp. 1173᎐1180, Nov. 1989.
6. C. H. Lam, ‘‘Virtual path traffic management of cross-path switch,’’ Ph.D. dissertation, Chinese University of Hong Kong, Jul. 1997.
7. T. T. Lee and S. Y. Liew, ‘‘Parallel algorithm for Benes networks,’’ Proc. IEEE INFOCOM ’96, Mar. 1996.
8. T. T. Lee and C. H. Lam, ‘‘Path switchingᎏA quasi-static routing scheme for large-scale ATM packet switches,’’ IEEE J. Select. Areas Commun., vol. 15, no. 5,
pp. 914᎐924, Jun. 1997. 9. F. T. Leighton, Introduction to Parallel Algorithms and Architectures: Arrays ⭈ Trees ⭈
Hypercubes, Morgan Kaufmann, 1992. 10. F. M. Chiussi, J. G. Kneuer, and V. P. Kumar, ‘‘Low-cost scalable switching
solutions for broadband networking: the ATLANTA architecture and chipset,’’ IEEE Commun. Mag., pp. 44᎐53, Dec. 1997.
11. N. Mckeown, ‘‘The iSLIP scheduling algorithm for input-queue Switches,’’ IEEE Trans. Networking, vol. 7, no. 2, pp. 188᎐200, Apr. 1999.
12. R. J. McEliece, R. B. Ash, and C. Ash, Introduction to Discrete Mathematics, McGraw-Hill, 1989.
13. N. Mckeown, ‘‘Scheduling algorithm for input-queued cell switches,’’ Ph.D. The- sis, University of California at Berkeley, 1995.
14. E. Oki, Z. Jing, R. Rojas-Cessa, and H. J. Chao, ‘‘Concurrent round-robin dispatching scheme in a Clos-network switch,’’ IEEE ICC 2001, pp. 107᎐112,
Helsinki, Finland, Jun. 2001. 15. R. J. Wilson, Introduction to Graph Theory, Academic Press, New York, 1972.
16. Y.-S. Yeh, M. G. Hluchyj, and A. S. Acampora, ‘‘The knockout switch: a simple, modular architecture for high-performance packet switching,’’ IEEE J. Select.
Areas Commun., vol. 5, no. 8, pp. 1274᎐1283, Oct. 1987.
H. Jonathan Chao, Cheuk H. Lam, Eiji Oki Copyright 䊚 2001 John Wiley Sons, Inc.
Ž .
Ž .
ISBNs: 0-471-00454-5 Hardback ; 0-471-22440-5 Electronic
CHAPTER 11
OPTICAL PACKET SWITCHES
Introduction of optical fibers to communication networks has caused a tremendous increase in the speed of data transmitted. The virtually unlimited
bandwidth of optical fibers comes from the carrier frequency of nearly 200 w x
w x
THz 1 . Optical networking technology, such as add-drop multiplexers 2, 3 , w x
reconfigurable photonic switches 4 , and wavelength division-multiplexing Ž
. w
x WDM , has progressed well and facilitated optical networking 5, 6 . Espe-
Ž .
cially, recent advances in dense wavelength multiplexing division DWDM technology have provided tremendous bandwidth in optical fiber communica-
w x tions 7 . However, the capability of switching and routing packets at this high
Ž .
bandwidth e.g., 1 Tbitrs has lagged far behind the transmission capability. Building a large-capacity packet switching system using only electronic tech-
nology may lead to a system bottleneck in interconnecting many electronic devices or modules, mainly caused by the enormous number of interconnec-
tion wires and the electromagnetic interference they would generate. With the advancement of optical devices technology, several packet switch archi-
tectures based on WDM technology have been proposed for large-capacity packet switches. Although today’s optical packet switching technology is still
very primitive and cannot compete with electronic switching technology, optical packet switches have great potential to scale up their switching
capacity as the technology of some key optical devices becomes mature.
A photonic packet switch requires optical devices such as lasers, filters, couplers, memories, multiplexers, and demultiplexers. At the present time,
some of these devices are either too power-consuming or too slow in switching to compete with electronic devices. However, it is possible to design
279
OPTICAL PACKET SWITCHES
280
high-capacity switches by the use of both electronic and optical technologies. In such switches, data transfer can be achieved through optical media, and
complicated functions such as contention resolution and routing control can be performed electronically. These switches are called hybrid switches.
Hybrid switches that only convert packet cell headers into electronics for processing and controlling and leave the entire cell to be handled in the
optical domain are called optically transparent.
The ongoing research in photonic ATM switches is to develop faster and larger optical switches and new techniques that can be used to enhance the
existing optical switch architectures. There are many issues to be considered when designing an optical packet switch, such as the characteristics of the
optical devices employed, scalability of the switch, power budget of the system, synchronization between electrical and incoming optical signals,
performance of the switch under various traffic patterns, and so on. In addition, some of the techniques developed for optical ATM switches might
be applied to large-scale ATM switches where small electronic ATM modules are interconnected by an optical interconnection network.
Ž .
The techniques of space-division multiplexing SDM , time-division multi- Ž
. plexing TDM , and WDM have been used in designing optical switches.
SDM requires a large number of binary switching elements. From the switch size and cost point of view, it is not an ideal approach for photonic switching.
w x TDM is a classical technique used in communications 8 . When it is applied
to optical switching, complicated temporal compression and temporal expan- sion circuits are required. The throughput of such a switch is limited by the
speed of the demultiplexer, which in practice is controlled by electronics for the time being.
WDM is made possible by the range of wavelengths on an optical fiber. It splits the optical bandwidth of a link into fixed, nonoverlapping spectral
bands. Each band has a wavelength channel that can be used for a specific bit rate and transmission technique, independent of the choices for other chan-
nels.
In this chapter, we review several approaches to building a large-capacity packet switch and discuss their advantages and disadvantages. These switch
Ž architectures are classified into all-optical packet switches
described in .
Ž .
Section 11.1 and optoelectronic packet switches described in Section 11.2 , depending on whether the contended packets are stored in the optical or in
the electrical domain. Two optical packet switches will be described in detail Ž
. Ž
in Sections 11.3 using optical memory and 11.4 using optics for intercon- .
nection only to better understand switching operations and implementation complexity. In all the architectures presented here, switch control is achieved
electronically, since for the time being it is complicated to realize logical operations optically. The capacity of electronic control units and the tuning
speed of optical devices are the main performance-limiting factors in these architectures.
ALL-OPTICAL PACKET SWITCHES
