BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
5.1 BANYAN NETWORKS
w x The banyan class of interconnection networks was originally defined in 9 . It has the property that there is exactly one path from any input to any output. 103 BANYAN-BASED SWITCHES 104 Ž . Ž . Fig. 5.1 Four different banyan-class networks: a shuffle-exchange omega net- Ž . Ž . Ž . work; b reverse shuffle-exchange network; c narrow-sense banyan network; d Ž . Ž . baseline network. We can see that a and b are isomorphic by interchanging the two shaded nodes. Figure 5.1 shows four networks belonging to this class: the shuffle-exchange Ž . network narrow-sense also called the omega network , the reverse shuffle- exchange network, the narrow-sense banyan network, and the baseline net- work. Ž . The principal common properties of these networks are: 1 they consist of 1 Ž . n s log N stages and Nr2 nodes per stage, 2 they have the self-routing 2 property that the unique n-bit destination address can be used to route a cell Ž . from any input to any output, each bit for one stage, and 3 their regularity and interconnection pattern are very attractive for VLSI implementation. Figure 5.2 shows a routing example in an 8 = 8 banyan network, where the bold lines indicate the routing paths. On the right hand side, the address of each output destination is labeled as a string of n bits, b ⭈⭈⭈ b . A cell’s 1 n destination address is encoded into the header of the cell. In the first stage, the most significant bit b is examined. If it is a 0, the cell will be forwarded 1 to the upper outgoing link; if it is a 1, the cell will be forwarded to the lower outgoing link. In the next stage, the next most significant bit b will be 2 1 A regular N = N network can also be constructed from identical b = b switching nodes in k stages, where N s b k . BANYAN NETWORKS 105 Fig. 5.2 An 8 = 8 banyan network. examined and the routing performed in the same manner. The internal blocking refers to the case where a cell is lost due to the contention on a link inside the network. Figure 5.3 shows an example of internal blocking in an 8 = 8 banyan network. However, the banyan network will be internally nonblocking if both conditions below are satisfied: 䢇 there is no idle input between any two active inputs; 䢇 the output addresses of the cells are in either ascending order or descending order. Fig. 5.3 Internal blocking in an 8 = 8 banyan network. BANYAN-BASED SWITCHES 106 Fig. 5.4 An example showing that the banyan network is nonblocking for sorted Ž . inputs. b Nonblocking sort᎐banyan network. See Figure 5.4. Suppose the banyan network is preceded by a network that concentrates the cells and sorts the cells according to their output destina- tions. The overall sort᎐banyan network will be internally nonblocking.5.2 BATCHER-SORTING NETWORK
Parts
» ATM Switch Structure ATM SWITCH SYSTEMS
» DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
» Internal Link Blocking Output Port Contention Head-of-Line Blocking
» Shared-Medium Switch Time-Division Switching
» Single-Path Switches Space-Division Switching
» Multiple-Path Switches Space-Division Switching
» Internally Buffered Switches Recirculation Buffered Switches
» Input- and Output-Buffered Switches Virtual-Output-Queueing Switches
» Input-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Completely Shared-Buffer Switches PERFORMANCE OF BASIC SWITCHES
» Bernoulli Arrival Process and Random Traffic On–Off Model and Bursty Traffic
» Multiline Input Smoothing Speedup Parallel Switch
» Window-Based Lookahead Selection Increasing Scheduling Efficiency
» VOQ-Based Matching Increasing Scheduling Efficiency
» Parallel Iterative Matching PIM Iterative Round-Robin Matching iRRM
» Iterative Round-Robin with SLIP i SLIP
» Dual Round-Robin Matching DRRM
» Round-Robin Greedy Scheduling SCHEDULING ALGORITHMS
» Bidirectional Arbiter Design of Round-Robin Arbiters r
» Token Tunneling This section introduces a more efficient arbi-
» Most-Urgent-Cell-First Algorithm MUCFA OUTPUT-QUEUING EMULATION
» Critical Cell First CCF Last In, Highest Priority LIHP
» LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST JONATHAN CHAO CHEUK LAM
» LINKED LIST APPROACH JONATHAN CHAO CHEUK LAM
» CONTENT-ADDRESSABLE MEMORY APPROACH JONATHAN CHAO CHEUK LAM
» Washington University Gigabit Switch
» Shared-Memory Switch with a Multicast Logical Queue Shared-Memory Switch with Cell Copy
» Shared-Memory Switch with Address Copy
» BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
» Three-Phase Implementation Ring Reservation
» BATCHER-SORTING NETWORK THE SUNSHINE SWITCH
» Tandem Banyan Switch DEFLECTION ROUTING
» Shuffle-Exchange Network with Deflection Routing
» Dual Shuffle-Exchange Network with Error-Correcting Routing
» Generalized Self-Routing Algorithm Broadcast Banyan Network
» Boolean Interval Splitting Algorithm Nonblocking Condition of Broadcast Banyan Networks A
» Encoding Process MULTICAST COPY NETWORKS
» Concentration Decoding Process Overflow and Call Splitting
» A. Cyclic Running Adder Network Figure 5.34 shows the struc-
» Concentration The starting point in a CRAN may not be port 0,
» Basic Architecture SINGLE-STAGE KNOCKOUT SWITCH
» Knockout Concentration Principle SINGLE-STAGE KNOCKOUT SWITCH
» Construction of the Concentrator
» Maximum Throughput CHANNEL GROUPING PRINCIPLE
» Two-Stage Configuration A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Multicast Grouping Network A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Translation Tables A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Cross-Stuck CS Fault Toggle-Stuck TS Fault Verticalr
» Toggle-Stuck and Cross-Stuck Cases
» Vertical-Stuck and Horizontal-Stuck Cases
» Cross-Stuck and Toggle-Stuck Cases
» Vertical-Stuck Case Horizontal-Stuck SWE Case
» APPENDIX JONATHAN CHAO CHEUK LAM
» BASIC ARCHITECTURE JONATHAN CHAO CHEUK LAM
» MULTICAST CONTENTION RESOLUTION ALGORITHM
» IMPLEMENTATION OF INPUT PORT CONTROLLER
» Cell Loss Probability PERFORMANCE
» ATM ROUTING AND CONCENTRATION CHIP
» Memoryless Multistage Concentration Network
» Buffered Multistage Concentration Network
» Resequencing Cells ENHANCED ABACUS SWITCH
» Complexity Comparison ENHANCED ABACUS SWITCH
» Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» Cell Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» MSDA Structure MULTIPLE-QOS SDA SWITCH
» OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES OVERVIEW OF INPUT
» Basic Architecture Unicasting Operation
» ROUTING PROPERTIES AND SCHEDULING METHODS
» A SUBOPTIMAL STRAIGHT MATCHING METHOD
» Basic Architecture Distributed and Random Arbitration
» Basic Architecture THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
» Concurrent Round-Robin Dispatching Scheme
» Homogeneous Capacity and Route Assignment
» The Staggering Switch ALL-OPTICAL PACKET SWITCHES
» HYPASS OPTOELECTRONIC PACKET SWITCHES
» STAR-TRACK OPTOELECTRONIC PACKET SWITCHES
» Cisneros and Brackett’s Architecture
» Basic Architecture THE 3M SWITCH
» Cell Delineation Unit THE 3M SWITCH
» VCI-Overwrite Unit Cell Synchronization Unit
» Input and Output Forwarding Engines Input and Output Switch Interfaces
» Route Controller Router Module and Route Controller
» Input Optical Module Output Optical Module Tunable Filters
» Principles of Ping-Pong Arbitration Consider an N-input
» Performance of PPA Implementation of PPA
» Priority PPA Ping-Pong Arbitration Unit
» Component Complexity OIN Complexity
» Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
» Crosstalk Analysis OPTICAL INTERCONNECTION NETWORK FOR
» System Considerations WIRELESS ATM STRUCTURE OVERVIEWS
» NEC’s WATMnet Prototype System
» Olivetti’s Radio ATM LAN Virtual Connection Tree
» BAHAMA Wireless ATM LAN NTT’s Wireless ATM Access
» Radio Physical Layer RADIO ACCESS LAYERS
» Medium Access Control Layer Data Link Control Layer
» Connection Rerouting HANDOFF IN WIRELESS ATM
» Buffering Cell Routing in a COS
» Design of a Mobility-Support Switch
» Performance MOBILITY-SUPPORT ATM SWITCH
» Architectures of Generic Routers
» IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE IP ROUTE LOOKUP BASED ON STANDARD
» Levels 2 and 3 of Data Structure
» Adapting Binary Search for Best-Matching Prefix
» Precomputed 16-Bit Prefix Table Multiway Binary Search: Exploiting the Cache Line
» Lookup Algorithms and Data Structure Construction
» Prefix Update Algorithms IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
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