Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
11.4.6.2 Interconnection Complexity
As a representative interconnec- tion complexity, the interconnection between the electronic controller and the 256 = 256 OIN is evaluated. The interconnection complexity of the proposed 256 = 256 OIN is determined by the number of the SOA gates in the OOMs. The types of tunable filters and the number of wavelengths applied to the OIN are two dominant factors of the interconnection complex- ity, because they determine the number of SOA gates in the OOMs. Because the interconnection complexity with type-I and type-II tunable filters is the same, only type-II and type-III tunable filters are considered in this regard. Figure 11.40 shows the interconnection complexity for different wave- Ž . lengths W s 8, 16, 32, and 64 and different types of tunable filters, where X is the complexity introduced by the switching fabrics, Y is the complexity represented by the tunable filters, and X q Y gives the total interconnection complexity. Type-I and type-II tunable filters have the same interconnection complexity. For example, if W s 16, X s Y s 256 = 4 when using type-I -II, or -III tunable filters. As shown in Figure 11.40, the total interconnection complexity, X q Y, is equal to 256 = 8, and is independent of the wavelength number and the type of tunable filter used in the OIN.11.4.7 Power Budget Analysis
Power loss in the OIN, which is due to splitting loss, depends on the number of wavelengths and the size of the switching fabric of each OOM. To compensate for power loss in the OIN, optical amplifiers, such as EDFAs Fig. 11.40 Interconnection complexity of the 256 = 256 OIN for different types of tunable filter and different wavelength numbers W. OPTICAL INTERCONNECTION NETWORK FOR TERABIT IP ROUTERS 327 and SOA gates, have to provide wide bandwidth to accommodate multiple wavelengths with uniform gain in the 1550-nm window. At each IOM, to avoid the problems introduced by direct modulation of lasers, such as large Ž . frequency chirp, an external modulator EM is used to obtain an optical Ž . on᎐off keying OOK signal. Figure 11.41 shows the optical signal path through the OIN with type-II tunable filters and W s 16. All the optical components are represented with their gains or losses. For simplicity of modeling and analysis, the OIN is assumed to be fully loaded and all the possible connections between the input᎐output pairs established. Second, optical signals are represented by their optical power corresponding to bit mark᎐space data signals. Third, frequency chirp due to the EM and dispersion effects of all the components are not taken into consideration since signals are transmitted only in the Fig. 11.41 Power budget of the 256 = 256 optical interconnection network with 16 Ž . Ž . wavelengths and type-II tunable filters: a before and b after power compensation by EDFA. OPTICAL PACKET SWITCHES 328 short-length fibers in the OIN. Finally, all the light reflections in the system are ignored and all the passive components are assumed to be polarization- insensitive. Ž . Figure 11.41 a shows that, without power compensation, the received power is only y30.5 dBm, much less than required sensitivity of about y20 Ž . y 12 dBm at the bit error rate BER of 10 for signals at 10 Gbitrs. To increase the received optical power, optical amplifiers are necessary to provide sufficient gain to compensate for the power loss in the OIN. In the proposed OIN, there are two kinds of optical amplifiers to perform the power compensation function. One is the SOA and the other is the EDFA. Ž . As shown in Figure 11,41 b , an EDFA with 10.5-dB gain at each IOM is used to amplify 16 wavelengths simultaneously, so that the sensitivity at the receiver is increased to y20 dBm. Note that the gain provided by the EDFA needs to be increased to 20 dB if the AWG, which is near the output link of type-II tunable filter, is replaced by a 16 = 1 combiner.11.4.8 Crosstalk Analysis
Parts
» ATM Switch Structure ATM SWITCH SYSTEMS
» DESIGN CRITERIA AND PERFORMANCE REQUIREMENTS
» Internal Link Blocking Output Port Contention Head-of-Line Blocking
» Shared-Medium Switch Time-Division Switching
» Single-Path Switches Space-Division Switching
» Multiple-Path Switches Space-Division Switching
» Internally Buffered Switches Recirculation Buffered Switches
» Input- and Output-Buffered Switches Virtual-Output-Queueing Switches
» Input-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Output-Buffered Switches PERFORMANCE OF BASIC SWITCHES
» Completely Shared-Buffer Switches PERFORMANCE OF BASIC SWITCHES
» Bernoulli Arrival Process and Random Traffic On–Off Model and Bursty Traffic
» Multiline Input Smoothing Speedup Parallel Switch
» Window-Based Lookahead Selection Increasing Scheduling Efficiency
» VOQ-Based Matching Increasing Scheduling Efficiency
» Parallel Iterative Matching PIM Iterative Round-Robin Matching iRRM
» Iterative Round-Robin with SLIP i SLIP
» Dual Round-Robin Matching DRRM
» Round-Robin Greedy Scheduling SCHEDULING ALGORITHMS
» Bidirectional Arbiter Design of Round-Robin Arbiters r
» Token Tunneling This section introduces a more efficient arbi-
» Most-Urgent-Cell-First Algorithm MUCFA OUTPUT-QUEUING EMULATION
» Critical Cell First CCF Last In, Highest Priority LIHP
» LOWEST-OUTPUT-OCCUPANCY-CELL-FIRST JONATHAN CHAO CHEUK LAM
» LINKED LIST APPROACH JONATHAN CHAO CHEUK LAM
» CONTENT-ADDRESSABLE MEMORY APPROACH JONATHAN CHAO CHEUK LAM
» Washington University Gigabit Switch
» Shared-Memory Switch with a Multicast Logical Queue Shared-Memory Switch with Cell Copy
» Shared-Memory Switch with Address Copy
» BANYAN NETWORKS JONATHAN CHAO CHEUK LAM
» Three-Phase Implementation Ring Reservation
» BATCHER-SORTING NETWORK THE SUNSHINE SWITCH
» Tandem Banyan Switch DEFLECTION ROUTING
» Shuffle-Exchange Network with Deflection Routing
» Dual Shuffle-Exchange Network with Error-Correcting Routing
» Generalized Self-Routing Algorithm Broadcast Banyan Network
» Boolean Interval Splitting Algorithm Nonblocking Condition of Broadcast Banyan Networks A
» Encoding Process MULTICAST COPY NETWORKS
» Concentration Decoding Process Overflow and Call Splitting
» A. Cyclic Running Adder Network Figure 5.34 shows the struc-
» Concentration The starting point in a CRAN may not be port 0,
» Basic Architecture SINGLE-STAGE KNOCKOUT SWITCH
» Knockout Concentration Principle SINGLE-STAGE KNOCKOUT SWITCH
» Construction of the Concentrator
» Maximum Throughput CHANNEL GROUPING PRINCIPLE
» Two-Stage Configuration A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Multicast Grouping Network A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Translation Tables A TWO-STAGE MULTICAST OUTPUT-BUFFERED ATM SWITCH
» Cross-Stuck CS Fault Toggle-Stuck TS Fault Verticalr
» Toggle-Stuck and Cross-Stuck Cases
» Vertical-Stuck and Horizontal-Stuck Cases
» Cross-Stuck and Toggle-Stuck Cases
» Vertical-Stuck Case Horizontal-Stuck SWE Case
» APPENDIX JONATHAN CHAO CHEUK LAM
» BASIC ARCHITECTURE JONATHAN CHAO CHEUK LAM
» MULTICAST CONTENTION RESOLUTION ALGORITHM
» IMPLEMENTATION OF INPUT PORT CONTROLLER
» Cell Loss Probability PERFORMANCE
» ATM ROUTING AND CONCENTRATION CHIP
» Memoryless Multistage Concentration Network
» Buffered Multistage Concentration Network
» Resequencing Cells ENHANCED ABACUS SWITCH
» Complexity Comparison ENHANCED ABACUS SWITCH
» Packet Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» Cell Interleaving ABACUS SWITCH FOR PACKET SWITCHING
» MSDA Structure MULTIPLE-QOS SDA SWITCH
» OVERVIEW OF CROSSPOINT-BUFFERED SWITCHES OVERVIEW OF INPUT
» Basic Architecture Unicasting Operation
» ROUTING PROPERTIES AND SCHEDULING METHODS
» A SUBOPTIMAL STRAIGHT MATCHING METHOD
» Basic Architecture Distributed and Random Arbitration
» Basic Architecture THE CONTINUOUS ROUND-ROBIN DISPATCHING SWITCH
» Concurrent Round-Robin Dispatching Scheme
» Homogeneous Capacity and Route Assignment
» The Staggering Switch ALL-OPTICAL PACKET SWITCHES
» HYPASS OPTOELECTRONIC PACKET SWITCHES
» STAR-TRACK OPTOELECTRONIC PACKET SWITCHES
» Cisneros and Brackett’s Architecture
» Basic Architecture THE 3M SWITCH
» Cell Delineation Unit THE 3M SWITCH
» VCI-Overwrite Unit Cell Synchronization Unit
» Input and Output Forwarding Engines Input and Output Switch Interfaces
» Route Controller Router Module and Route Controller
» Input Optical Module Output Optical Module Tunable Filters
» Principles of Ping-Pong Arbitration Consider an N-input
» Performance of PPA Implementation of PPA
» Priority PPA Ping-Pong Arbitration Unit
» Component Complexity OIN Complexity
» Power Budget Analysis OPTICAL INTERCONNECTION NETWORK FOR
» Crosstalk Analysis OPTICAL INTERCONNECTION NETWORK FOR
» System Considerations WIRELESS ATM STRUCTURE OVERVIEWS
» NEC’s WATMnet Prototype System
» Olivetti’s Radio ATM LAN Virtual Connection Tree
» BAHAMA Wireless ATM LAN NTT’s Wireless ATM Access
» Radio Physical Layer RADIO ACCESS LAYERS
» Medium Access Control Layer Data Link Control Layer
» Connection Rerouting HANDOFF IN WIRELESS ATM
» Buffering Cell Routing in a COS
» Design of a Mobility-Support Switch
» Performance MOBILITY-SUPPORT ATM SWITCH
» Architectures of Generic Routers
» IP ROUTE LOOKUP BASED ON CACHING TECHNIQUE IP ROUTE LOOKUP BASED ON STANDARD
» Levels 2 and 3 of Data Structure
» Adapting Binary Search for Best-Matching Prefix
» Precomputed 16-Bit Prefix Table Multiway Binary Search: Exploiting the Cache Line
» Lookup Algorithms and Data Structure Construction
» Prefix Update Algorithms IP ROUTE LOOKUPS USING TWO-TRIE STRUCTURE
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